Ngā tūemi rite

• Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
  mā: Paulin, Gianna, me ētahi atu.
  I whakaputaina: (2024)
• Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
  mā: Scheffler, Paul, me ētahi atu.
  I whakaputaina: (2025)
• Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores
  mā: Colagrande, Luca, me ētahi atu.
  I whakaputaina: (2026)
• Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
  mā: Colagrande, Luca, me ētahi atu.
  I whakaputaina: (2025)
• SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
  mā: Scheffler, Paul, me ētahi atu.
  I whakaputaina: (2024)