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Bibliographic Details
Main Authors:	Schmulbach, Viansa, Kim, Jason, Gao, Ethan, Revina, Lucy, Jha, Nikhil, Wu, Ethan, Nikolic, Borivoje
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2503.14708
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Table of Contents:

This paper introduces NeCTAr (Near-Cache Transformer Accelerator), a 16nm heterogeneous multicore RISC-V SoC for sparse and dense machine learning kernels with both near-core and near-memory accelerators. A prototype chip runs at 400MHz at 0.85V and performs matrix-vector multiplications with 109 GOPs/W. The effectiveness of the design is demonstrated by running inference on a sparse language model, ReLU-Llama.