Uloženo v:
| Hlavní autoři: | , , , , , , , , , , |
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| Médium: | Preprint |
| Vydáno: |
2026
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| Témata: | |
| On-line přístup: | https://arxiv.org/abs/2604.06607 |
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Obsah:
- LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.