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| Main Authors: | , , , , , , , , , , , , , , |
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| Format: | Recurso digital |
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Zenodo
2025
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| Online Access: | https://doi.org/10.5281/zenodo.14676264 |
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Table of Contents:
- <h2>[2025.1.0]</h2> <h3>Added</h3> <ul> <li><p><strong>Architecture</strong></p> <ul> <li>New accelerator interface for fine-grained data access control (#237)</li> <li>Support for multiple simultaneous multicast messages (#247)</li> </ul> </li> <li><p><strong>Infrastructure</strong></p> <ul> <li>New linting scripts and GitHub actions flow (#242)</li> </ul> </li> <li><p><strong>Software</strong></p> <ul> <li>Example multicore baremetal application</li> </ul> </li> </ul> <h3>Improved</h3> <ul> <li><p><strong>Architecture</strong></p> <ul> <li>Support for up to 256 tiles and 512 APB devices</li> <li>Moved NoC routers to top level of hierarchy (#238)</li> <li>Support for up to 16 CPU tiles and 16 memory tiles</li> <li>Make number of cache ways more flexible</li> <li>Expand number of accelerator registers to 128</li> <li>Restrict unavailable accelerator coherence modes from HW</li> </ul> </li> <li><p><strong>Infrastructure</strong></p> <ul> <li>Support for up to 7 DDR controllers on proFPGA-xcvu19p board</li> <li>Linted all C, C++, Python, Verilog, and System Verilog files</li> </ul> </li> </ul> <h3>Fixed</h3> <ul> <li><p><strong>Accelerator Design Flows</strong></p> <ul> <li>Fixed matchlib dependencies for Catapult HLS SystemC flow (#241)</li> </ul> </li> <li><p><strong>Architecture</strong></p> <ul> <li>Resolved synthesis warnings in caches and router</li> <li>Fixed a bug in DMA busy state of noc2ahbm module</li> </ul> </li> <li><p><strong>Infrastructure</strong></p> <ul> <li>Fixed issue in handling a large number of RTL files (#232)</li> </ul> </li> </ul>