R, V. N., & Hiremath, S. (2022). Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level. Zenodo.
Chicago Style (17th ed.) CitationR, Vibha Narayan, and Sujatha Hiremath. Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level. Zenodo, 2022.
MLA (9th ed.) CitationR, Vibha Narayan, and Sujatha Hiremath. Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level. Zenodo, 2022.
Warning: These citations may not always be 100% accurate.