Saved in:
Bibliographic Details
Main Author: Rasque, Chadwick
Format: Recurso digital
Language:English
Published: Zenodo 2026
Subjects:
Online Access:https://doi.org/10.5281/zenodo.18462613
Tags: Add Tag
No Tags, Be the first to tag this record!
Table of Contents:
  • <p></p> <p>Classical thermal models treat heat in CPUs as resistive loss or energy dissipation. In the MID/QC framework, heat is reinterpreted as <strong>tension collapse</strong> within the quantized substrate: a coherence‑level failure mode that emerges when routing, switching, or substrate geometry exceed local coherence‑preservation capacity. This paper develops the substrate‑native thermal model that unifies heating, throttling, leakage, and breakdown as coherence‑gradient phenomena rather than material constraints. The result is a predictive architecture for thermal limits in CPUs grounded in substrate tension dynamics.</p> <p></p>