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| Main Author: | |
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| Format: | Recurso digital |
| Language: | English |
| Published: |
Zenodo
2026
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| Subjects: | |
| Online Access: | https://doi.org/10.5281/zenodo.18462613 |
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Table of Contents:
- <p></p> <p>Classical thermal models treat heat in CPUs as resistive loss or energy dissipation. In the MID/QC framework, heat is reinterpreted as <strong>tension collapse</strong> within the quantized substrate: a coherence‑level failure mode that emerges when routing, switching, or substrate geometry exceed local coherence‑preservation capacity. This paper develops the substrate‑native thermal model that unifies heating, throttling, leakage, and breakdown as coherence‑gradient phenomena rather than material constraints. The result is a predictive architecture for thermal limits in CPUs grounded in substrate tension dynamics.</p> <p></p>