Míreanna comhchosúla

• RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis
  de réir: Lau, Jason, et al.
  Foilsithe / Cruthaithe: (2024)
• FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration
  de réir: Zhu, Shien, et al.
  Foilsithe / Cruthaithe: (2026)
• Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
  de réir: Li, Yinrong, et al.
  Foilsithe / Cruthaithe: (2026)
• Efficient and Scalable Architecture for Multiple-chip Implementation of Simulated Bifurcation Machines
  de réir: Kashimata, Tomoya, et al.
  Foilsithe / Cruthaithe: (2023)
• $Δ$-Nets: Interaction-Based System for Optimal Parallel $λ$-Reduction
  de réir: Salvadori, Daniel Augusto Rizzi
  Foilsithe / Cruthaithe: (2025)