Image de couverture de livre

Rainbow: A Composable Coherence Protocol for Multi-Chip Servers

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Menezo, Lucia G., Puente, Valentin, Gregorio, Jose A.
Format:	Preprint
Publié:	2020
Sujets:	Hardware Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

CLAASIC: a Cortex-Inspired Hardware Accelerator
par: Puente, Valentin, et autres
Publié: (2016)

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
par: Sheikh, Ahmad T., et autres
Publié: (2024)

Composing Mini Oscilloscope on Embedded Systems
par: Romero, Brennan, et autres
Publié: (2025)

Limited Read-Write/Set Hardware Transactional Memory without modifying the ISA or the Coherence Protocol
par: Kafousis, Konstantinos
Publié: (2025)

Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
par: Huang, Zongle, et autres
Publié: (2026)

An opportunity to improve Data Center Efficiency: Optimizing the Server's Upgrade Cycle
par: Nikolaou, Panagiota, et autres
Publié: (2025)

Salient Store: Enabling Smart Storage for Continuous Learning Edge Servers
par: Mishra, Cyan Subhra, et autres
Publié: (2024)

MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
par: Raj, Ritik, et autres
Publié: (2025)

CIS: Composable Instruction Set for Data Streaming Applications
par: Yang, Yu, et autres
Publié: (2024)

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
par: Park, Haneul, et autres
Publié: (2025)

Large Processor Chip Model
par: Chang, Kaiyan, et autres
Publié: (2025)

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering
par: Jamet, Alexandre Valentin, et autres
Publié: (2024)

Resilient and Secure Programmable System-on-Chip Accelerator Offload
par: Gouveia, Inês Pinto, et autres
Publié: (2024)

Garibaldi: A Pairwise Instruction-Data Management for Enhancing Shared Last-Level Cache Performance in Server Workloads
par: Kwon, Jaewon, et autres
Publié: (2025)

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
par: Chen, Xingzhen, et autres
Publié: (2026)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
par: Shih, Yu-An, et autres
Publié: (2025)

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers
par: Antoniou, Georgia, et autres
Publié: (2022)

A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
par: Gao, Yizhao, et autres
Publié: (2024)

WIP: Turning Fake Chips into Learning Opportunities
par: Mehraban, Haniye, et autres
Publié: (2025)

LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems
par: Ye, Bochen, et autres
Publié: (2025)

AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications
par: Yahya, Jawad Haj, et autres
Publié: (2022)

HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV
par: Shijie, Liu, et autres
Publié: (2026)

Improving Chip Design Enablement for Universities in Europe -- A Position Paper
par: Krupp, Lukas, et autres
Publié: (2025)

Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
par: Ainsworth, Sam, et autres
Publié: (2024)

Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits
par: Jin, Haoran, et autres
Publié: (2025)

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
par: McDougall, Ian, et autres
Publié: (2025)

A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
par: Zhou, Wenyong, et autres
Publié: (2025)

Algorithm-Driven On-Chip Integration for High Density and Low Cost
par: Kim, Jeongeun, et autres
Publié: (2025)

EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations
par: Choi, Sangun, et autres
Publié: (2025)

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
par: Zuckerman, Joseph, et autres
Publié: (2024)

Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
par: Zhao, Hongwei, et autres
Publié: (2025)

3D MPSoC with On-Chip Cache Support -- Design and Exploitation
par: Cataldo, Rodrigo, et autres
Publié: (2025)

Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips
par: Chen, Peilin, et autres
Publié: (2025)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
par: Fang, Wenji, et autres
Publié: (2025)

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization
par: ouyang, Yikang, et autres
Publié: (2026)

Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip
par: Zaeemi, Meysam, et autres
Publié: (2026)

FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
par: Tong, Jianming, et autres
Publié: (2024)

Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs
par: Bochem, Severin, et autres
Publié: (2024)

Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
par: Zhu, Jingchen, et autres
Publié: (2024)

TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips
par: Wang, Huizheng, et autres
Publié: (2025)