ALIGN: A System for Automating Analog Layout
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arXiv
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| Main Authors: | , , , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2020
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| _version_ | 1866915747916152832 |
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| author | Dhar, Tonmoy Kunal, Kishor Li, Yaguang Madhusudan, Meghna Poojary, Jitesh Sharma, Arvind K. Xu, Wenbin Burns, Steven M. Harjani, Ramesh Hu, Jiang Kirkpatrick, Desmond A. Mukherjee, Parijat Sapatnekar, Sachin S. Yaldiz, Soner |
| author_facet | Dhar, Tonmoy Kunal, Kishor Li, Yaguang Madhusudan, Meghna Poojary, Jitesh Sharma, Arvind K. Xu, Wenbin Burns, Steven M. Harjani, Ramesh Hu, Jiang Kirkpatrick, Desmond A. Mukherjee, Parijat Sapatnekar, Sachin S. Yaldiz, Soner |
| contents | ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2008_10682 |
| institution | arXiv |
| publishDate | 2020 |
| record_format | arxiv |
| spellingShingle | ALIGN: A System for Automating Analog Layout Dhar, Tonmoy Kunal, Kishor Li, Yaguang Madhusudan, Meghna Poojary, Jitesh Sharma, Arvind K. Xu, Wenbin Burns, Steven M. Harjani, Ramesh Hu, Jiang Kirkpatrick, Desmond A. Mukherjee, Parijat Sapatnekar, Sachin S. Yaldiz, Soner Hardware Architecture ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits. |
| title | ALIGN: A System for Automating Analog Layout |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2008.10682 |