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| Main Authors: | , |
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| Format: | Preprint |
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2021
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2107.13053 |
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| _version_ | 1866917816574148608 |
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| author | Hua, Yuanyuan Chitnis, Danial |
| author_facet | Hua, Yuanyuan Chitnis, Danial |
| contents | Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-0.998, -1.533] for time resolution of 5.00 ps, [-0.44,0.49] for 10.04 ps, [-0.16, 0.19] for 21.65 ps, [-0.10, 0.11] for 43.87 ps, [-0.06, 0.07] for 64.12 ps, and [-0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To our knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2107_13053 |
| institution | arXiv |
| publishDate | 2021 |
| record_format | arxiv |
| spellingShingle | A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter Hua, Yuanyuan Chitnis, Danial Systems and Control Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-0.998, -1.533] for time resolution of 5.00 ps, [-0.44,0.49] for 10.04 ps, [-0.16, 0.19] for 21.65 ps, [-0.10, 0.11] for 43.87 ps, [-0.06, 0.07] for 64.12 ps, and [-0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To our knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs. |
| title | A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2107.13053 |