METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
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arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2021
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| _version_ | 1866929718324887552 |
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| author | Wang, Zhao Zhu, Jingchen Zhou, Zhe Sun, Guangyu |
| author_facet | Wang, Zhao Zhu, Jingchen Zhou, Zhe Sun, Guangyu |
| contents | Tiled spatial architectures have proved to be an effective solution to build large-scale DNN accelerators. In particular, interconnections between tiles are critical for high performance in these tile-based architectures. In this work, we identify the inefficiency of the widely used traditional on-chip networks and the opportunity of software-hardware co-design. We propose METRO with the basic idea of decoupling the traffic scheduling policies from hardware fabrics and moving them to the software level. METRO contains two modules working in synergy: METRO software scheduling framework to coordinate the traffics and METRO hardware facilities to deliver the data based on software configurations. We evaluate the co-design using different flit sizes for synthetic study, illustrating its effectiveness under various hardware resource constraints, in addition to a wide range of DNN models selected from real-world workloads. The results show that METRO achieves 56.3% communication speedup on average and up to 73.6% overall processing time reduction compared with traditional on-chip network designs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2108_10570 |
| institution | arXiv |
| publishDate | 2021 |
| record_format | arxiv |
| spellingShingle | METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators Wang, Zhao Zhu, Jingchen Zhou, Zhe Sun, Guangyu Hardware Architecture Tiled spatial architectures have proved to be an effective solution to build large-scale DNN accelerators. In particular, interconnections between tiles are critical for high performance in these tile-based architectures. In this work, we identify the inefficiency of the widely used traditional on-chip networks and the opportunity of software-hardware co-design. We propose METRO with the basic idea of decoupling the traffic scheduling policies from hardware fabrics and moving them to the software level. METRO contains two modules working in synergy: METRO software scheduling framework to coordinate the traffics and METRO hardware facilities to deliver the data based on software configurations. We evaluate the co-design using different flit sizes for synthetic study, illustrating its effectiveness under various hardware resource constraints, in addition to a wide range of DNN models selected from real-world workloads. The results show that METRO achieves 56.3% communication speedup on average and up to 73.6% overall processing time reduction compared with traditional on-chip network designs. |
| title | METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2108.10570 |