Saved in:
| Main Authors: | , |
|---|---|
| Format: | Preprint |
| Published: |
2021
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2112.05924 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866910292166836224 |
|---|---|
| author | Krishna, Komala Nambath, Nandakumar |
| author_facet | Krishna, Komala Nambath, Nandakumar |
| contents | Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2112_05924 |
| institution | arXiv |
| publishDate | 2021 |
| record_format | arxiv |
| spellingShingle | Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS Krishna, Komala Nambath, Nandakumar Systems and Control Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V. |
| title | Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2112.05924 |