Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
Fuente:
arXiv
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| Autori principali: | , |
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| Natura: | Preprint |
| Pubblicazione: |
2022
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| _version_ | 1866912001080426496 |
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| author | Feng, Yinxiao Ma, Kaisheng |
| author_facet | Feng, Yinxiao Ma, Kaisheng |
| contents | Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2203_12268 |
| institution | arXiv |
| publishDate | 2022 |
| record_format | arxiv |
| spellingShingle | Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration Feng, Yinxiao Ma, Kaisheng Hardware Architecture Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture. |
| title | Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2203.12268 |