Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning
Fuente:
arXiv
Saved in:
| Main Authors: | Kumar, Pratik, Nandi, Ankita, Chakrabartty, Shantanu, Thakur, Chetan Singh |
|---|---|
| Format: | Preprint |
| Published: |
2022
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
KALAM: toolKit for Automating high-Level synthesis of Analog computing systeMs
by: Nandi, Ankita, et al.
Published: (2024)
by: Nandi, Ankita, et al.
Published: (2024)
RRAM-Based Analog Matrix Computing for Massive MIMO Signal Processing: A Review
by: Zuo, Pushen, et al.
Published: (2025)
by: Zuo, Pushen, et al.
Published: (2025)
SpecPCM: A Low-power PCM-based In-Memory Computing Accelerator for Full-stack Mass Spectrometry Analysis
by: Fan, Keming, et al.
Published: (2024)
by: Fan, Keming, et al.
Published: (2024)
Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
by: Rizzo, Tommaso, et al.
Published: (2024)
by: Rizzo, Tommaso, et al.
Published: (2024)
A scalable event-driven spatiotemporal feature extraction circuit
by: Greatorex, Hugh, et al.
Published: (2025)
by: Greatorex, Hugh, et al.
Published: (2025)
AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG
by: Shi, Yichen, et al.
Published: (2024)
by: Shi, Yichen, et al.
Published: (2024)
Recent Advances in mm-Wave and Sub-THz/THz Oscillators for FutureG Technologies
by: Behmanesh, Baktash, et al.
Published: (2026)
by: Behmanesh, Baktash, et al.
Published: (2026)
2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology
by: Kuriakose, Neethu, et al.
Published: (2025)
by: Kuriakose, Neethu, et al.
Published: (2025)
SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems
by: Razmkhah, Sasan, et al.
Published: (2024)
by: Razmkhah, Sasan, et al.
Published: (2024)
Scalable Digital Compute-in-Memory Ising Machines for Robustness Verification of Binary Neural Networks
by: Vadlamani, Madhav, et al.
Published: (2026)
by: Vadlamani, Madhav, et al.
Published: (2026)
AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding
by: Kim, Seungmin, et al.
Published: (2026)
by: Kim, Seungmin, et al.
Published: (2026)
Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine
by: Gonul, Yilmaz Ege, et al.
Published: (2025)
by: Gonul, Yilmaz Ege, et al.
Published: (2025)
Fault-Free Analog Computing with Imperfect Hardware
by: Xu, Zhicheng, et al.
Published: (2025)
by: Xu, Zhicheng, et al.
Published: (2025)
Current Opinions on Memristor-Accelerated Machine Learning Hardware
by: Jiang, Mingrui, et al.
Published: (2025)
by: Jiang, Mingrui, et al.
Published: (2025)
Evaluating Computing Platforms for Sustainability: A Comparative Analysis of FPGAs against ASICs, GPUs, and CPUs
by: Sudarshan, Chetan Choppali, et al.
Published: (2026)
by: Sudarshan, Chetan Choppali, et al.
Published: (2026)
Digital Signal Processing from Classical Coherent Systems to Continuous-Variable QKD: A Review of Cross-Domain Techniques, Applications, and Challenges
by: de Sousa, Davi Juvêncio Gomes, et al.
Published: (2025)
by: de Sousa, Davi Juvêncio Gomes, et al.
Published: (2025)
Scalable Connectivity for Ising Machines: Dense to Sparse
by: Sajeeb, M Mahmudul Hasan, et al.
Published: (2025)
by: Sajeeb, M Mahmudul Hasan, et al.
Published: (2025)
Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads
by: Lokhande, Mukul, et al.
Published: (2025)
by: Lokhande, Mukul, et al.
Published: (2025)
A Reconfigurable Time-Domain In-Memory Computing Macro using FeFET-Based CAM with Multilevel Delay Calibration in 28 nm CMOS
by: Mattar, Jeries, et al.
Published: (2025)
by: Mattar, Jeries, et al.
Published: (2025)
Parallel Tempering-Inspired Distributed Binary Optimization with In-Memory Computing
by: Zhang, Xiangyi, et al.
Published: (2024)
by: Zhang, Xiangyi, et al.
Published: (2024)
Accelerating Hybrid XOR$-$CNF Boolean Satisfiability Problems Natively with In-Memory Computing
by: Im, Haesol, et al.
Published: (2025)
by: Im, Haesol, et al.
Published: (2025)
PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro with In-Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout
by: Chen, Zhiyu, et al.
Published: (2024)
by: Chen, Zhiyu, et al.
Published: (2024)
NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors
by: Nair, Harideep, et al.
Published: (2024)
by: Nair, Harideep, et al.
Published: (2024)
Function Approximation Using Analog Building Blocks in Flexible Electronics
by: Duarte, Paula Carolina Lozano, et al.
Published: (2025)
by: Duarte, Paula Carolina Lozano, et al.
Published: (2025)
CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems
by: Sudarshan, Chetan Choppali, et al.
Published: (2026)
by: Sudarshan, Chetan Choppali, et al.
Published: (2026)
Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits
by: Pallavi, CH., et al.
Published: (2024)
by: Pallavi, CH., et al.
Published: (2024)
Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips
by: Onizawa, Naoya, et al.
Published: (2026)
by: Onizawa, Naoya, et al.
Published: (2026)
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
by: Ferro, Elena, et al.
Published: (2024)
by: Ferro, Elena, et al.
Published: (2024)
The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
by: Chen, Lei, et al.
Published: (2024)
by: Chen, Lei, et al.
Published: (2024)
Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy
by: Wang, Xiaoke, et al.
Published: (2025)
by: Wang, Xiaoke, et al.
Published: (2025)
All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices
by: Falcone, Donato Francesco, et al.
Published: (2025)
by: Falcone, Donato Francesco, et al.
Published: (2025)
ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
by: Chen, Hanqiu, et al.
Published: (2024)
by: Chen, Hanqiu, et al.
Published: (2024)
Leveraging AES Padding: dBs for Nothing and FEC for Free in IoT Systems
by: Woo, Jongchan, et al.
Published: (2024)
by: Woo, Jongchan, et al.
Published: (2024)
A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge
by: Papandroulidakis, Georgios, et al.
Published: (2024)
by: Papandroulidakis, Georgios, et al.
Published: (2024)
GRAMC: General-purpose and reconfigurable analog matrix computing architecture
by: Pan, Lunshuai, et al.
Published: (2025)
by: Pan, Lunshuai, et al.
Published: (2025)
Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits
by: Zhang, Xiameng, et al.
Published: (2026)
by: Zhang, Xiameng, et al.
Published: (2026)
Novel Efficient Scalable QCA XOR and Full Adder Designs
by: Safaiezadeh, Behrouz, et al.
Published: (2023)
by: Safaiezadeh, Behrouz, et al.
Published: (2023)
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits
by: Chen, Yibo, et al.
Published: (2025)
by: Chen, Yibo, et al.
Published: (2025)
Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories
by: Choudhary, Yousuf, et al.
Published: (2026)
by: Choudhary, Yousuf, et al.
Published: (2026)
RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration
by: Zhao, Lei, et al.
Published: (2023)
by: Zhao, Lei, et al.
Published: (2023)
Similar Items
-
KALAM: toolKit for Automating high-Level synthesis of Analog computing systeMs
by: Nandi, Ankita, et al.
Published: (2024) -
RRAM-Based Analog Matrix Computing for Massive MIMO Signal Processing: A Review
by: Zuo, Pushen, et al.
Published: (2025) -
SpecPCM: A Low-power PCM-based In-Memory Computing Accelerator for Full-stack Mass Spectrometry Analysis
by: Fan, Keming, et al.
Published: (2024) -
Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
by: Rizzo, Tommaso, et al.
Published: (2024) -
A scalable event-driven spatiotemporal feature extraction circuit
by: Greatorex, Hugh, et al.
Published: (2025)