Toward A Formalized Approach for Spike Sorting Algorithms and Hardware Evaluation
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2022
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| _version_ | 1866909469309403136 |
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| author | Zhang, Tim Lammie, Corey Azghadi, Mostafa Rahimi Amirsoleimani, Amirali Ahmadi, Majid Genov, Roman |
| author_facet | Zhang, Tim Lammie, Corey Azghadi, Mostafa Rahimi Amirsoleimani, Amirali Ahmadi, Majid Genov, Roman |
| contents | Spike sorting algorithms are used to separate extracellular recordings of neuronal populations into single-unit spike activities. The development of customized hardware implementing spike sorting algorithms is burgeoning. However, there is a lack of a systematic approach and a set of standardized evaluation criteria to facilitate direct comparison of both software and hardware implementations. In this paper, we formalize a set of standardized criteria and a publicly available synthetic dataset entitled Synthetic Simulations Of Extracellular Recordings (SSOER), which was constructed by aggregating existing synthetic datasets with varying Signal-To-Noise Ratios (SNRs). Furthermore, we present a benchmark for future comparison, and use our criteria to evaluate a simulated Resistive Random-Access Memory (RRAM) In-Memory Computing (IMC) system using the Discrete Wavelet Transform (DWT) for feature extraction. Our system consumes approximately (per channel) 10.72mW and occupies an area of 0.66mm$^2$ in a 22nm FDSOI Complementary Metal-Oxide-Semiconductor (CMOS) process. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2205_06514 |
| institution | arXiv |
| publishDate | 2022 |
| record_format | arxiv |
| spellingShingle | Toward A Formalized Approach for Spike Sorting Algorithms and Hardware Evaluation Zhang, Tim Lammie, Corey Azghadi, Mostafa Rahimi Amirsoleimani, Amirali Ahmadi, Majid Genov, Roman Machine Learning Hardware Architecture Performance Spike sorting algorithms are used to separate extracellular recordings of neuronal populations into single-unit spike activities. The development of customized hardware implementing spike sorting algorithms is burgeoning. However, there is a lack of a systematic approach and a set of standardized evaluation criteria to facilitate direct comparison of both software and hardware implementations. In this paper, we formalize a set of standardized criteria and a publicly available synthetic dataset entitled Synthetic Simulations Of Extracellular Recordings (SSOER), which was constructed by aggregating existing synthetic datasets with varying Signal-To-Noise Ratios (SNRs). Furthermore, we present a benchmark for future comparison, and use our criteria to evaluate a simulated Resistive Random-Access Memory (RRAM) In-Memory Computing (IMC) system using the Discrete Wavelet Transform (DWT) for feature extraction. Our system consumes approximately (per channel) 10.72mW and occupies an area of 0.66mm$^2$ in a 22nm FDSOI Complementary Metal-Oxide-Semiconductor (CMOS) process. |
| title | Toward A Formalized Approach for Spike Sorting Algorithms and Hardware Evaluation |
| topic | Machine Learning Hardware Architecture Performance |
| url | https://arxiv.org/abs/2205.06514 |