ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key
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arXiv
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| Main Authors: | , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2022
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| _version_ | 1866909070155317248 |
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| author | Wang, Jianfeng Chen, Zhonghao Zhang, Jiahao Xu, Yixin Yu, Tongguang Ye, Enze Zheng, Ziheng Yang, Huazhong George, Sumitha Liu, Yongpan Narayanan, Vijaykrishnan Li, Xueqing |
| author_facet | Wang, Jianfeng Chen, Zhonghao Zhang, Jiahao Xu, Yixin Yu, Tongguang Ye, Enze Zheng, Ziheng Yang, Huazhong George, Sumitha Liu, Yongpan Narayanan, Vijaykrishnan Li, Xueqing |
| contents | Intellectual property (IP) piracy has become a non-negligible problem as the integrated circuit (IC) production supply chain is becoming increasingly globalized and separated that enables attacks by potentially untrusted attackers. Logic locking is a widely adopted method to lock the circuit module with a key and prevent hackers from cracking it. The key is the critical aspect of logic locking, but the existing works have overlooked three possible challenges of the key: safety of key storage, easy key-attempt from interface and key-related overheads, bringing the further challenges of low error rate and small state space. In this work, the key is dynamically generated by utilizing the huge space of a CPU core, and the unlocking is performed implicitly through the interconnection inside the chip. A novel low-cost logic reconfigurable gate is together proposed with ferroelectric FET (FeFET) to mitigate the reverse engineering and removal attack. Compared to the common logic locking methods, our proposed approach is 19,945 times more time consuming to traverse all the possible combinations in only 9-bit-key condition. Furthermore, our technique let key length increases this complexity exponentially and ensure the logic obfuscation effect. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2206_08087 |
| institution | arXiv |
| publishDate | 2022 |
| record_format | arxiv |
| spellingShingle | ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key Wang, Jianfeng Chen, Zhonghao Zhang, Jiahao Xu, Yixin Yu, Tongguang Ye, Enze Zheng, Ziheng Yang, Huazhong George, Sumitha Liu, Yongpan Narayanan, Vijaykrishnan Li, Xueqing Hardware Architecture B.2.3; B.6.2; B.7.3 Intellectual property (IP) piracy has become a non-negligible problem as the integrated circuit (IC) production supply chain is becoming increasingly globalized and separated that enables attacks by potentially untrusted attackers. Logic locking is a widely adopted method to lock the circuit module with a key and prevent hackers from cracking it. The key is the critical aspect of logic locking, but the existing works have overlooked three possible challenges of the key: safety of key storage, easy key-attempt from interface and key-related overheads, bringing the further challenges of low error rate and small state space. In this work, the key is dynamically generated by utilizing the huge space of a CPU core, and the unlocking is performed implicitly through the interconnection inside the chip. A novel low-cost logic reconfigurable gate is together proposed with ferroelectric FET (FeFET) to mitigate the reverse engineering and removal attack. Compared to the common logic locking methods, our proposed approach is 19,945 times more time consuming to traverse all the possible combinations in only 9-bit-key condition. Furthermore, our technique let key length increases this complexity exponentially and ensure the logic obfuscation effect. |
| title | ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key |
| topic | Hardware Architecture B.2.3; B.6.2; B.7.3 |
| url | https://arxiv.org/abs/2206.08087 |