Designing Approximate Arithmetic Circuits with Combined Error Constraints
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2022
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| _version_ | 1866914106593771520 |
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| author | Češka, Milan Matyáš, Jiří Mrazek, Vojtech Vojnar, Tomáš |
| author_facet | Češka, Milan Matyáš, Jiří Mrazek, Vojtech Vojnar, Tomáš |
| contents | Approximate circuits trading the power consumption for the quality of results play a key role in the development of energy-aware systems. Designing complex approximate circuits is, however, a very difficult and computationally demanding process. When deploying approximate circuits, various error metrics (e.g., mean average error, worst-case error, error rate), as well as other constraints (e.g., correct multiplication by 0), have to be considered. The state-of-the-art approximation methods typically focus on a single metric which significantly limits the applicability of the resulting circuits. In this paper, we experimentally investigate how various error metrics and their combinations affect the reduction of the power consumption that can be achieved. To this end, we extend evolutionary-driven techniques that allow us to effectively explore the design space of the approximate circuits. We identify principal limitations when complex error constraints are required as well as important correlations among the error metrics enabling the construction of circuits providing the best-known trade-offs between the power reduction and combined error constraints. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2206_13077 |
| institution | arXiv |
| publishDate | 2022 |
| record_format | arxiv |
| spellingShingle | Designing Approximate Arithmetic Circuits with Combined Error Constraints Češka, Milan Matyáš, Jiří Mrazek, Vojtech Vojnar, Tomáš Hardware Architecture Approximate circuits trading the power consumption for the quality of results play a key role in the development of energy-aware systems. Designing complex approximate circuits is, however, a very difficult and computationally demanding process. When deploying approximate circuits, various error metrics (e.g., mean average error, worst-case error, error rate), as well as other constraints (e.g., correct multiplication by 0), have to be considered. The state-of-the-art approximation methods typically focus on a single metric which significantly limits the applicability of the resulting circuits. In this paper, we experimentally investigate how various error metrics and their combinations affect the reduction of the power consumption that can be achieved. To this end, we extend evolutionary-driven techniques that allow us to effectively explore the design space of the approximate circuits. We identify principal limitations when complex error constraints are required as well as important correlations among the error metrics enabling the construction of circuits providing the best-known trade-offs between the power reduction and combined error constraints. |
| title | Designing Approximate Arithmetic Circuits with Combined Error Constraints |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2206.13077 |