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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2022
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2207.11728 |
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| _version_ | 1866916337760075776 |
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| author | Shin, Taeho Lee, Dongjun Kim, Dongwhee Sung, Gaeryun Shin, Wookjin Jo, Yunseong Park, Hyungjoo Han, Jaeduk |
| author_facet | Shin, Taeho Lee, Dongjun Kim, Dongwhee Sung, Gaeryun Shin, Wookjin Jo, Yunseong Park, Hyungjoo Han, Jaeduk |
| contents | This paper presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology with the following additional techniques applied to produce optimal layouts more effectively. First, layout templates and grids are dynamically created and adjusted during runtime to serve various structural, functional, and design requirements. Virtual instances support the dynamic template-and-grid-based layout generation process. The framework also implements various post-processing functions to handle process-specific requirements efficiently. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description capability is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to various design examples and generates DRC/LVS clean layouts automatically in multiple CMOS technologies. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2207_11728 |
| institution | arXiv |
| publishDate | 2022 |
| record_format | arxiv |
| spellingShingle | A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids Shin, Taeho Lee, Dongjun Kim, Dongwhee Sung, Gaeryun Shin, Wookjin Jo, Yunseong Park, Hyungjoo Han, Jaeduk Signal Processing Hardware Architecture This paper presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology with the following additional techniques applied to produce optimal layouts more effectively. First, layout templates and grids are dynamically created and adjusted during runtime to serve various structural, functional, and design requirements. Virtual instances support the dynamic template-and-grid-based layout generation process. The framework also implements various post-processing functions to handle process-specific requirements efficiently. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description capability is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to various design examples and generates DRC/LVS clean layouts automatically in multiple CMOS technologies. |
| title | A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids |
| topic | Signal Processing Hardware Architecture |
| url | https://arxiv.org/abs/2207.11728 |