Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2022
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866914870684811264 |
|---|---|
| author | Unger, Josua Messinger, Anette Niehoff, Benjamin E. Fellner, Michael Lechner, Wolfgang |
| author_facet | Unger, Josua Messinger, Anette Niehoff, Benjamin E. Fellner, Michael Lechner, Wolfgang |
| contents | We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2211_11287 |
| institution | arXiv |
| publishDate | 2022 |
| record_format | arxiv |
| spellingShingle | Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization Unger, Josua Messinger, Anette Niehoff, Benjamin E. Fellner, Michael Lechner, Wolfgang Quantum Physics We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line. |
| title | Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization |
| topic | Quantum Physics |
| url | https://arxiv.org/abs/2211.11287 |