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A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface

Fuente: arXiv

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Détails bibliographiques
Auteurs principaux:	Yin, Guodong, Zhou, Mufeng, Chen, Yiming, Tang, Wenjun, Yang, Zekun, Lee, Mingyen, Du, Xirui, Yue, Jinshan, Liu, Jiaxin, Yang, Huazhong, Liu, Yongpan, Li, Xueqing
Format:	Preprint
Publié:	2022
Sujets:	Hardware Architecture Machine Learning
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

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