Reconfigurable Radar Signal Processing Accelerator for Integrated Sensing and Communication System
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| Main Authors: | , , , , |
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| Format: | Preprint |
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2023
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| _version_ | 1866913466091044864 |
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| author | Tewari, Aakanksha Jha, Shragvi Sidharth Sneh, Akanksha Darak, Sumit J Ram, Shobha Sundar |
| author_facet | Tewari, Aakanksha Jha, Shragvi Sidharth Sneh, Akanksha Darak, Sumit J Ram, Shobha Sundar |
| contents | IEEE 802.11ad-based integrated sensing and communications (ISAC) have been identified as a potential solution for enabling next-generation intelligent transportation systems in the millimeter wave (mmW) spectrum. The radar functionality within the ISAC enables accurate detection and localization of mobile targets, which can significantly speed up the selection of the optimal high-directional narrow beam required for mmW communications between the base station and mobile target. To bring ISAC to reality, a radar signal processing (RSP) accelerator, co-located with the wireless communication physical layer (PHY), on edge platforms, is desired. In this work, we discuss the three-dimensional digital hardware RSP framework for 802.11ad-based ISAC to detect the range, azimuth, and Doppler velocity of multiple targets. We present an efficient reconfigurable architecture for RSP on multi-processor system-on-chip (MPSoC) via hardware-software co-design, word-length optimization, and serial-parallel configurations. We demonstrate the functional correctness of the proposed fixed-point architecture and significant savings in resource utilization (40-70%), execution time (1.5x improvement), and power consumption (50%) over floating-point architecture. The acceleration on hardware offers a 120-factor improvement in execution time over the benchmark Quad-core processor. The proposed architecture enables on-the-fly reconfigurability to support different azimuth precision and Doppler velocity resolution, offering a real-time trade-off between functional accuracy and detection time. We implement end-to-end ISAC comprising RSP and PHY on MPSoC and demonstrate significant improvement in throughput over IEEE 802.11ad. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2303_01702 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Reconfigurable Radar Signal Processing Accelerator for Integrated Sensing and Communication System Tewari, Aakanksha Jha, Shragvi Sidharth Sneh, Akanksha Darak, Sumit J Ram, Shobha Sundar Signal Processing IEEE 802.11ad-based integrated sensing and communications (ISAC) have been identified as a potential solution for enabling next-generation intelligent transportation systems in the millimeter wave (mmW) spectrum. The radar functionality within the ISAC enables accurate detection and localization of mobile targets, which can significantly speed up the selection of the optimal high-directional narrow beam required for mmW communications between the base station and mobile target. To bring ISAC to reality, a radar signal processing (RSP) accelerator, co-located with the wireless communication physical layer (PHY), on edge platforms, is desired. In this work, we discuss the three-dimensional digital hardware RSP framework for 802.11ad-based ISAC to detect the range, azimuth, and Doppler velocity of multiple targets. We present an efficient reconfigurable architecture for RSP on multi-processor system-on-chip (MPSoC) via hardware-software co-design, word-length optimization, and serial-parallel configurations. We demonstrate the functional correctness of the proposed fixed-point architecture and significant savings in resource utilization (40-70%), execution time (1.5x improvement), and power consumption (50%) over floating-point architecture. The acceleration on hardware offers a 120-factor improvement in execution time over the benchmark Quad-core processor. The proposed architecture enables on-the-fly reconfigurability to support different azimuth precision and Doppler velocity resolution, offering a real-time trade-off between functional accuracy and detection time. We implement end-to-end ISAC comprising RSP and PHY on MPSoC and demonstrate significant improvement in throughput over IEEE 802.11ad. |
| title | Reconfigurable Radar Signal Processing Accelerator for Integrated Sensing and Communication System |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2303.01702 |