Cover Image

Diba: A Re-configurable Stream Processor

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Najafi, Mohammadreza, Qadah, Thamir M., Sadoghi, Mohammad, Jacobsen, Hans-Arno
Format:	Preprint
Published:	2023
Subjects:	Databases Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Enthuse: Efficient Adaptable High-throughput Streaming Aggregation Engines
by: Papaphilippou, Philippos, et al.
Published: (2024)

SwiftSpatial: Spatial Joins on Modern Hardware
by: Jiang, Wenqi, et al.
Published: (2023)

SpANNS: Optimizing Approximate Nearest Neighbor Search for Sparse Vectors Using Near Memory Processing
by: Zhang, Tianqi, et al.
Published: (2026)

HDDB: Efficient In-Storage SQL Database Search Using Hyperdimensional Computing on Ferroelectric NAND Flash
by: Zhao, Quanling, et al.
Published: (2025)

Analyzing Performance Characteristics of PostgreSQL and MariaDB on NVMeVirt
by: Han, Juhee, et al.
Published: (2024)

GraphMatch: Subgraph Query Processing on FPGAs
by: Dann, Jonas, et al.
Published: (2024)

JSPIM: A Skew-Aware PIM Accelerator for High-Performance Databases Join and Select Operations
by: Tajdari, Sabiha, et al.
Published: (2025)

Accelerating String-Key Learned Index Structures via Memoization-based Incremental Training
by: Kim, Minsu, et al.
Published: (2024)

Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs
by: Allison, Michael, et al.
Published: (2025)

Qute: Towards Quantum-Native Database
by: Chen, Muzhi, et al.
Published: (2026)

A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors
by: Kuper, Reese, et al.
Published: (2023)

MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
by: Jiang, Zhe, et al.
Published: (2025)

SAMIPS: A Synthesised Asynchronous Processor
by: Zhang, Qianyi, et al.
Published: (2024)

Large Processor Chip Model
by: Chang, Kaiyan, et al.
Published: (2025)

PIMDAL: Mitigating the Memory Bottleneck in Data Analytics using a Real Processing-in-Memory System
by: Frouzakis, Manos, et al.
Published: (2025)

A 950 MHz SIMT Soft Processor
by: Langhammer, Martin, et al.
Published: (2025)

Power- and Area-Efficient Unary Sorting Architecture Using FSM-Based Unary Number Generator
by: Jalilvand, Amir Hossein, et al.
Published: (2025)

Banked Memories for Soft SIMT Processors
by: Langhammer, Martin, et al.
Published: (2025)

Memory Hierarchy Design for Caching Middleware in the Age of NVM
by: Ghandeharizadeh, Shahram, et al.
Published: (2025)

Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
by: Rezunov, Evgenii, et al.
Published: (2025)

Duet: Creating Harmony between Processors and Embedded FPGAs
by: Li, Ang, et al.
Published: (2023)

Implementation of Compute Intensive Algorithms on Software Configurable Processor
by: Ganesha, et al.
Published: (2025)

Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
by: Harlikar, Pracheta, et al.
Published: (2025)

Don't Persist All : Efficient Persistent Data Structures
by: Mahapatra, Pratyush, et al.
Published: (2019)

Image processing Application Development on Software Configurable Processor Array
by: Prabhu, Ganesh, et al.
Published: (2025)

Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)

Loop Control Management in Tightly Coupled Processor Arrays (TCPAs)
by: Walter, Dominik, et al.
Published: (2026)

Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)

ARAS: An Adaptive Low-Cost ReRAM-Based Accelerator for DNNs
by: Sabri, Mohammad, et al.
Published: (2024)

LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
by: Moon, Seungjae, et al.
Published: (2024)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
by: Colagrande, Luca, et al.
Published: (2025)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025)

Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs
by: Walter, Dominik, et al.
Published: (2025)

AGON: Automated Design Framework for Customizing Processors from ISA Documents
by: Li, Chongxiao, et al.
Published: (2024)

On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors
by: Behboudi, Noushin, et al.
Published: (2024)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)

TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)