Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)

Fuente: arXiv

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Bibliographic Details
Main Authors:	Kaiser, Md Abdullah-Al, Datta, Gourav, Sarkar, Sreetama, Kundu, Souvik, Yin, Zihan, Garg, Manas, Jacob, Ajey P., Beerel, Peter A., Jaiswal, Akhilesh R.
Format:	Preprint
Published:	2023
Subjects:	Image and Video Processing Hardware Architecture
Online Access:	Acceder al recurso
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author	Kaiser, Md Abdullah-Al Datta, Gourav Sarkar, Sreetama Kundu, Souvik Yin, Zihan Garg, Manas Jacob, Ajey P. Beerel, Peter A. Jaiswal, Akhilesh R.
author_facet	Kaiser, Md Abdullah-Al Datta, Gourav Sarkar, Sreetama Kundu, Souvik Yin, Zihan Garg, Manas Jacob, Ajey P. Beerel, Peter A. Jaiswal, Akhilesh R.
contents	The massive amounts of data generated by camera sensors motivate data processing inside pixel arrays, i.e., at the extreme-edge. Several critical developments have fueled recent interest in the processing-in-pixel-in-memory paradigm for a wide range of visual machine intelligence tasks, including (1) advances in 3D integration technology to enable complex processing inside each pixel in a 3D integrated manner while maintaining pixel density, (2) analog processing circuit techniques for massively parallel low-energy in-pixel computations, and (3) algorithmic techniques to mitigate non-idealities associated with analog processing through hardware-aware training schemes. This article presents a comprehensive technology-circuit-algorithm landscape that connects technology capabilities, circuit design strategies, and algorithmic optimizations to power, performance, area, bandwidth reduction, and application-level accuracy metrics. We present our results using a comprehensive co-design framework incorporating hardware and algorithmic optimizations for various complex real-life visual intelligence tasks mapped onto our P2M paradigm.
format	Preprint
id	arxiv_https___arxiv_org_abs_2304_02968
institution	arXiv
publishDate	2023
record_format	arxiv
spellingShingle	Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M) Kaiser, Md Abdullah-Al Datta, Gourav Sarkar, Sreetama Kundu, Souvik Yin, Zihan Garg, Manas Jacob, Ajey P. Beerel, Peter A. Jaiswal, Akhilesh R. Image and Video Processing Hardware Architecture The massive amounts of data generated by camera sensors motivate data processing inside pixel arrays, i.e., at the extreme-edge. Several critical developments have fueled recent interest in the processing-in-pixel-in-memory paradigm for a wide range of visual machine intelligence tasks, including (1) advances in 3D integration technology to enable complex processing inside each pixel in a 3D integrated manner while maintaining pixel density, (2) analog processing circuit techniques for massively parallel low-energy in-pixel computations, and (3) algorithmic techniques to mitigate non-idealities associated with analog processing through hardware-aware training schemes. This article presents a comprehensive technology-circuit-algorithm landscape that connects technology capabilities, circuit design strategies, and algorithmic optimizations to power, performance, area, bandwidth reduction, and application-level accuracy metrics. We present our results using a comprehensive co-design framework incorporating hardware and algorithmic optimizations for various complex real-life visual intelligence tasks mapped onto our P2M paradigm.
title	Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)
topic	Image and Video Processing Hardware Architecture
url	https://arxiv.org/abs/2304.02968