DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2023
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| _version_ | 1866929213551935488 |
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| author | Sonnino, Lorenzo Shresthamali, Shaswot He, Yuan Kondo, Masaaki |
| author_facet | Sonnino, Lorenzo Shresthamali, Shaswot He, Yuan Kondo, Masaaki |
| contents | DNNs are widely used but face significant computational costs due to matrix multiplications, especially from data movement between the memory and processing units. One promising approach is therefore Processing-in-Memory as it greatly reduces this overhead. However, most PIM solutions rely either on novel memory technologies that have yet to mature or bit-serial computations that have significant performance overhead and scalability issues. Our work proposes an in-SRAM digital multiplier, that uses a conventional memory to perform bit-parallel computations, leveraging multiple wordlines activation. We then introduce DAISM, an architecture leveraging this multiplier, which achieves up to two orders of magnitude higher area efficiency compared to the SOTA counterparts, with competitive energy efficiency. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2305_07376 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference Sonnino, Lorenzo Shresthamali, Shaswot He, Yuan Kondo, Masaaki Hardware Architecture Machine Learning DNNs are widely used but face significant computational costs due to matrix multiplications, especially from data movement between the memory and processing units. One promising approach is therefore Processing-in-Memory as it greatly reduces this overhead. However, most PIM solutions rely either on novel memory technologies that have yet to mature or bit-serial computations that have significant performance overhead and scalability issues. Our work proposes an in-SRAM digital multiplier, that uses a conventional memory to perform bit-parallel computations, leveraging multiple wordlines activation. We then introduce DAISM, an architecture leveraging this multiplier, which achieves up to two orders of magnitude higher area efficiency compared to the SOTA counterparts, with competitive energy efficiency. |
| title | DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2305.07376 |