Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2023
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866929304356519936 |
|---|---|
| author | Shen, Shan Xu, Hao Zhou, Yongliang Ling, Ming Yu, Wenjian |
| author_facet | Shen, Shan Xu, Hao Zhou, Yongliang Ling, Ming Yu, Wenjian |
| contents | In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256x64 array in 28nm CMOS technology. Post-simulations show successful read operation at 0.25V with 1.11μs read delay, and the minimum energy required is 1.69pJ at 0.4V. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2306_08936 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection Shen, Shan Xu, Hao Zhou, Yongliang Ling, Ming Yu, Wenjian Hardware Architecture In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256x64 array in 28nm CMOS technology. Post-simulations show successful read operation at 0.25V with 1.11μs read delay, and the minimum energy required is 1.69pJ at 0.4V. |
| title | Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2306.08936 |