An Introduction to the Compute Express Link (CXL) Interconnect
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2023
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| _version_ | 1866917660310110208 |
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| author | Sharma, Debendra Das Blankenship, Robert Berger, Daniel S. |
| author_facet | Sharma, Debendra Das Blankenship, Robert Berger, Daniel S. |
| contents | The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics with bandwidth that scales with PCIe bandwidth while achieving significantly lower latency than PCIe. All major CPU vendors, device vendors, and datacenter operators have adopted CXL as a common standard. This enables an inter-operable ecosystem that supports key computing use cases including highly efficient accelerators, server memory bandwidth and capacity expansion, multi-server resource pooling and sharing, and efficient peer-to-peer communication. This survey provides an introduction to CXL covering the standards CXL 1.0, CXL 2.0, and CXL 3.0. We further survey CXL implementations, discuss CXL's impact on the datacenter landscape, and future directions. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2306_11227 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | An Introduction to the Compute Express Link (CXL) Interconnect Sharma, Debendra Das Blankenship, Robert Berger, Daniel S. Hardware Architecture Operating Systems The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics with bandwidth that scales with PCIe bandwidth while achieving significantly lower latency than PCIe. All major CPU vendors, device vendors, and datacenter operators have adopted CXL as a common standard. This enables an inter-operable ecosystem that supports key computing use cases including highly efficient accelerators, server memory bandwidth and capacity expansion, multi-server resource pooling and sharing, and efficient peer-to-peer communication. This survey provides an introduction to CXL covering the standards CXL 1.0, CXL 2.0, and CXL 3.0. We further survey CXL implementations, discuss CXL's impact on the datacenter landscape, and future directions. |
| title | An Introduction to the Compute Express Link (CXL) Interconnect |
| topic | Hardware Architecture Operating Systems |
| url | https://arxiv.org/abs/2306.11227 |