Spatially resolved dielectric loss at the Si/SiO$_2$ interface
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2023
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| _version_ | 1866929303473618944 |
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| author | Cowie, Megan Stock, Taylor J. Z. Constantinou, Procopios C. Curson, Neil Grütter, Peter |
| author_facet | Cowie, Megan Stock, Taylor J. Z. Constantinou, Procopios C. Curson, Neil Grütter, Peter |
| contents | The Si/SiO$_2$ interface is populated by isolated trap states which modify its electronic properties. These traps are of critical interest for the development of semiconductor-based quantum sensors and computers, as well as nanoelectronic devices. Here, we study the electric susceptibility of the Si/SiO$_2$ interface with nm spatial resolution using frequency-modulated atomic force microscopy to measure a patterned dopant delta-layer buried 2 nm beneath the silicon native oxide interface. We show that surface charge organization timescales, which range from 1-150 ns, increase significantly around interfacial states. We conclude that dielectric loss under time-varying gate biases at MHz and sub-MHz frequencies in metal-insulator-semiconductor capacitor device architectures is highly spatially heterogeneous over nm length scales.
Supplemental GIFs can be found at https://doi.org/10.6084/m9.figshare.25546687 |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2306_13648 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Spatially resolved dielectric loss at the Si/SiO$_2$ interface Cowie, Megan Stock, Taylor J. Z. Constantinou, Procopios C. Curson, Neil Grütter, Peter Materials Science The Si/SiO$_2$ interface is populated by isolated trap states which modify its electronic properties. These traps are of critical interest for the development of semiconductor-based quantum sensors and computers, as well as nanoelectronic devices. Here, we study the electric susceptibility of the Si/SiO$_2$ interface with nm spatial resolution using frequency-modulated atomic force microscopy to measure a patterned dopant delta-layer buried 2 nm beneath the silicon native oxide interface. We show that surface charge organization timescales, which range from 1-150 ns, increase significantly around interfacial states. We conclude that dielectric loss under time-varying gate biases at MHz and sub-MHz frequencies in metal-insulator-semiconductor capacitor device architectures is highly spatially heterogeneous over nm length scales. Supplemental GIFs can be found at https://doi.org/10.6084/m9.figshare.25546687 |
| title | Spatially resolved dielectric loss at the Si/SiO$_2$ interface |
| topic | Materials Science |
| url | https://arxiv.org/abs/2306.13648 |