A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware
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arXiv
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| Main Authors: | Zhang, Shichang, Sohrabizadeh, Atefeh, Wan, Cheng, Huang, Zijie, Hu, Ziniu, Wang, Yewen, Yingyan, Lin, Cong, Jason, Sun, Yizhou |
|---|---|
| Format: | Preprint |
| Published: |
2023
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| Subjects: | |
| Online Access: | |
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