Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures
Fuente:
arXiv
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| Autore principale: | |
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| Natura: | Preprint |
| Pubblicazione: |
2023
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| _version_ | 1866916645945999360 |
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| author | Halder, Dipal |
| author_facet | Halder, Dipal |
| contents | The globalization of semiconductor supply chains has exposed Network-on-Chip (NoC) interconnects in System-on-Chip (SoC) architectures to critical security risks, including reverse engineering and IP theft. To address these threats, this work builds on two methodologies: ObNoCs [11], which obfuscates NoC topologies using programmable multiplexers, and POTENT [10], which enhances post-synthesis security against SAT-based attacks. These techniques ensure robust protection of NoC interconnects with minimal performance overhead. As the industry shifts to chiplet-based heterogeneous architectures, this research extends ObNoCs and POTENT to secure intra- and inter-chiplet interconnects. New challenges, such as safeguarding inter-chiplet communication and interposer design, are addressed through enhanced obfuscation, authentication, and encryption mechanisms. Experimental results demonstrate the practicality of these approaches for high-security applications, ensuring trust and reliability in monolithic and modular systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2307_05815 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures Halder, Dipal Cryptography and Security Hardware Architecture The globalization of semiconductor supply chains has exposed Network-on-Chip (NoC) interconnects in System-on-Chip (SoC) architectures to critical security risks, including reverse engineering and IP theft. To address these threats, this work builds on two methodologies: ObNoCs [11], which obfuscates NoC topologies using programmable multiplexers, and POTENT [10], which enhances post-synthesis security against SAT-based attacks. These techniques ensure robust protection of NoC interconnects with minimal performance overhead. As the industry shifts to chiplet-based heterogeneous architectures, this research extends ObNoCs and POTENT to secure intra- and inter-chiplet interconnects. New challenges, such as safeguarding inter-chiplet communication and interposer design, are addressed through enhanced obfuscation, authentication, and encryption mechanisms. Experimental results demonstrate the practicality of these approaches for high-security applications, ensuring trust and reliability in monolithic and modular systems. |
| title | Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2307.05815 |