PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender
Fuente:
arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2023
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866910447249129472 |
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| author | Li, Luyi Huang, Jiayi Feng, Lang Wang, Zhongfeng |
| author_facet | Li, Luyi Huang, Jiayi Feng, Lang Wang, Zhongfeng |
| contents | Cache side channel attacks are increasingly alarming in modern processors due to the recent emergence of Spectre and Meltdown attacks. A typical attack performs intentional cache access and manipulates cache states to leak secrets by observing the victim's cache access patterns. Different countermeasures have been proposed to defend against both general and transient execution based attacks. Despite their effectiveness, they mostly trade some level of performance for security, or have restricted security scope. In this paper, we seek an approach to enforcing security while maintaining performance. We leverage the insight that attackers need to access cache in order to manipulate and observe cache state changes for information leakage. Specifically, we propose Prefender, a secure prefetcher that learns and predicts attack-related accesses for prefetching the cachelines to simultaneously help security and performance. Our results show that Prefender is effective against several cache side channel attacks while maintaining or even improving performance for SPEC CPU 2006 and 2017 benchmarks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2307_06756 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender Li, Luyi Huang, Jiayi Feng, Lang Wang, Zhongfeng Hardware Architecture Cache side channel attacks are increasingly alarming in modern processors due to the recent emergence of Spectre and Meltdown attacks. A typical attack performs intentional cache access and manipulates cache states to leak secrets by observing the victim's cache access patterns. Different countermeasures have been proposed to defend against both general and transient execution based attacks. Despite their effectiveness, they mostly trade some level of performance for security, or have restricted security scope. In this paper, we seek an approach to enforcing security while maintaining performance. We leverage the insight that attackers need to access cache in order to manipulate and observe cache state changes for information leakage. Specifically, we propose Prefender, a secure prefetcher that learns and predicts attack-related accesses for prefetching the cachelines to simultaneously help security and performance. Our results show that Prefender is effective against several cache side channel attacks while maintaining or even improving performance for SPEC CPU 2006 and 2017 benchmarks. |
| title | PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2307.06756 |