Design and Performance of HV CMOS Sensors for Future Colliders by the RD50 Collaboration
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arXiv
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| Natura: | Preprint |
| Pubblicazione: |
2023
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| _version_ | 1866917773442023424 |
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| author | Sonneveld, Jory |
| author_facet | Sonneveld, Jory |
| contents | The CERN RD50 collaboration develops depleted monolithic active pixel CMOS sensors for future colliders with the aim of high radiation tolerance, good time resolution, and high granularity pixel detectors. The most recent prototype, the RD50-MPW3, is a 150 nm High Voltage CMOS LFoundry chip that features pixels with a 62 $μ$m pitch that integrate both digital and analog readout electronics inside the sensing diodes. The 64 x 64 pixels on this chip are arranged in 32 double columns and have an optimized periphery for efficient configuration and fast serial data transmission. Post-layout simulations of a single pixel show a power consumption of 22 $μ$W per pixel and 9 ns time walk. The predecessor of this version, the RD50-MPW2, was shown to match simulation results in tests at beam facilities and to have a time resolution of 300 ps both before and after irradiation to a fluence of $Φ_{\mathrm{eq}} = 5\cdot 10^{14}/\mathrm{cm}^2$. This proceeding discusses the design of the latest advanced prototype, the RD50-MPW3, the first results for the RD50-MPW3, and the performance of the RD50-MPW2. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2307_08600 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Design and Performance of HV CMOS Sensors for Future Colliders by the RD50 Collaboration Sonneveld, Jory Instrumentation and Detectors The CERN RD50 collaboration develops depleted monolithic active pixel CMOS sensors for future colliders with the aim of high radiation tolerance, good time resolution, and high granularity pixel detectors. The most recent prototype, the RD50-MPW3, is a 150 nm High Voltage CMOS LFoundry chip that features pixels with a 62 $μ$m pitch that integrate both digital and analog readout electronics inside the sensing diodes. The 64 x 64 pixels on this chip are arranged in 32 double columns and have an optimized periphery for efficient configuration and fast serial data transmission. Post-layout simulations of a single pixel show a power consumption of 22 $μ$W per pixel and 9 ns time walk. The predecessor of this version, the RD50-MPW2, was shown to match simulation results in tests at beam facilities and to have a time resolution of 300 ps both before and after irradiation to a fluence of $Φ_{\mathrm{eq}} = 5\cdot 10^{14}/\mathrm{cm}^2$. This proceeding discusses the design of the latest advanced prototype, the RD50-MPW3, the first results for the RD50-MPW3, and the performance of the RD50-MPW2. |
| title | Design and Performance of HV CMOS Sensors for Future Colliders by the RD50 Collaboration |
| topic | Instrumentation and Detectors |
| url | https://arxiv.org/abs/2307.08600 |