HiHGNN: Accelerating HGNNs through Parallelism and Data Reusability Exploitation
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arXiv
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| Main Authors: | Xue, Runzhen, Han, Dengke, Yan, Mingyu, Zou, Mo, Yang, Xiaocheng, Wang, Duo, Li, Wenming, Tang, Zhimin, Kim, John, Ye, Xiaochun, Fan, Dongrui |
|---|---|
| Format: | Preprint |
| Published: |
2023
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| Subjects: | |
| Online Access: | |
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