Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology
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arXiv
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| Format: | Preprint |
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2023
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| _version_ | 1866916149367668736 |
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| author | Hyun, Bongjoon Kim, Taehun Lee, Dongjae Rhu, Minsoo |
| author_facet | Hyun, Bongjoon Kim, Taehun Lee, Dongjae Rhu, Minsoo |
| contents | Processing-in-memory (PIM) has been explored for decades by computer architects, yet it has never seen the light of day in real-world products due to their high design overheads and lack of a killer application. With the advent of critical memory-intensive workloads, several commercial PIM technologies have been introduced to the market ranging from domain-specific PIM architectures to more general-purpose PIM architectures. In this work, we deepdive into UPMEM's commercial PIM technology, a general-purpose PIM-enabled parallel architecture that is highly programmable. Our first key contribution is the development of a flexible simulation framework for PIM. The simulator we developed (aka PIMulator) enables the compilation of UPMEM-PIM source codes into its compiled machine-level instructions, which are subsequently consumed by our cycle-level performance simulator. Using PIMulator, we demystify UPMEM's PIM design through a detailed characterization study. Building on top of our characterization, we conduct a series of case studies to pathfind important architectural features that we deem will be critical for future PIM architectures to support |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2308_00846 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology Hyun, Bongjoon Kim, Taehun Lee, Dongjae Rhu, Minsoo Hardware Architecture Processing-in-memory (PIM) has been explored for decades by computer architects, yet it has never seen the light of day in real-world products due to their high design overheads and lack of a killer application. With the advent of critical memory-intensive workloads, several commercial PIM technologies have been introduced to the market ranging from domain-specific PIM architectures to more general-purpose PIM architectures. In this work, we deepdive into UPMEM's commercial PIM technology, a general-purpose PIM-enabled parallel architecture that is highly programmable. Our first key contribution is the development of a flexible simulation framework for PIM. The simulator we developed (aka PIMulator) enables the compilation of UPMEM-PIM source codes into its compiled machine-level instructions, which are subsequently consumed by our cycle-level performance simulator. Using PIMulator, we demystify UPMEM's PIM design through a detailed characterization study. Building on top of our characterization, we conduct a series of case studies to pathfind important architectural features that we deem will be critical for future PIM architectures to support |
| title | Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2308.00846 |