parti-gem5: gem5's Timing Mode Parallelised
Fuente:
arXiv
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Preprint |
| Veröffentlicht: |
2023
|
| Schlagworte: | |
| Online-Zugang: | |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| _version_ | 1866917663142313984 |
|---|---|
| author | Cubero-Cascante, José Zurstraßen, Niko Nöller, Jörn Leupers, Rainer Joseph, Jan Moritz |
| author_facet | Cubero-Cascante, José Zurstraßen, Niko Nöller, Jörn Leupers, Rainer Joseph, Jan Moritz |
| contents | Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in memory hierarchies and interconnect topologies is also growing, making accurate predictions of design decisions more challenging than ever. In this context, the open-source Full System Simulator (FSS) gem5 is a popular choice for MPSoC design space exploration, thanks to its flexibility and robust set of detailed timing models. However, its single-threaded simulation kernel severely hampers its throughput. To address this challenge, we introduce parti-gem5, an extension of gem5 that enables parallel timing simulations on modern multi-core simulation hosts. Unlike previous works, parti-gem5 supports gem5's timing mode, the O3CPU, and Ruby's custom cache and interconnect models. Compared to reference single-thread simulations, we achieved speedups of up to 42.7x when simulating a 120-core ARM MPSoC on a 64-core x86-64 host system. While our method introduces timing deviations, the error in total simulated time is below 15% in most cases. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2308_09445 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | parti-gem5: gem5's Timing Mode Parallelised Cubero-Cascante, José Zurstraßen, Niko Nöller, Jörn Leupers, Rainer Joseph, Jan Moritz Hardware Architecture I.6.0 Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in memory hierarchies and interconnect topologies is also growing, making accurate predictions of design decisions more challenging than ever. In this context, the open-source Full System Simulator (FSS) gem5 is a popular choice for MPSoC design space exploration, thanks to its flexibility and robust set of detailed timing models. However, its single-threaded simulation kernel severely hampers its throughput. To address this challenge, we introduce parti-gem5, an extension of gem5 that enables parallel timing simulations on modern multi-core simulation hosts. Unlike previous works, parti-gem5 supports gem5's timing mode, the O3CPU, and Ruby's custom cache and interconnect models. Compared to reference single-thread simulations, we achieved speedups of up to 42.7x when simulating a 120-core ARM MPSoC on a 64-core x86-64 host system. While our method introduces timing deviations, the error in total simulated time is below 15% in most cases. |
| title | parti-gem5: gem5's Timing Mode Parallelised |
| topic | Hardware Architecture I.6.0 |
| url | https://arxiv.org/abs/2308.09445 |