PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
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arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2023
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| _version_ | 1866929238499655680 |
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| author | Andronic, Marta Constantinides, George A. |
| author_facet | Andronic, Marta Constantinides, George A. |
| contents | Field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with minimal overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2309_02334 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference Andronic, Marta Constantinides, George A. Machine Learning Hardware Architecture Field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with minimal overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset. |
| title | PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference |
| topic | Machine Learning Hardware Architecture |
| url | https://arxiv.org/abs/2309.02334 |