AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling

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Main Authors: Sahoo, Siva Satyendra, Ullah, Salim, Bhattacharjee, Soumyo, Kumar, Akash
Format: Preprint
Published: 2023
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author Sahoo, Siva Satyendra
Ullah, Salim
Bhattacharjee, Soumyo
Kumar, Akash
author_facet Sahoo, Siva Satyendra
Ullah, Salim
Bhattacharjee, Soumyo
Kumar, Akash
contents The rising usage of AI and ML-based processing across application domains has exacerbated the need for low-cost ML implementation, specifically for resource-constrained embedded systems. To this end, approximate computing, an approach that explores the power, performance, area (PPA), and behavioral accuracy (BEHAV) trade-offs, has emerged as a possible solution for implementing embedded machine learning. Due to the predominance of MAC operations in ML, designing platform-specific approximate arithmetic operators forms one of the major research problems in approximate computing. Recently there has been a rising usage of AI/ML-based design space exploration techniques for implementing approximate operators. However, most of these approaches are limited to using ML-based surrogate functions for predicting the PPA and BEHAV impact of a set of related design decisions. While this approach leverages the regression capabilities of ML methods, it does not exploit the more advanced approaches in ML. To this end, we propose AxOCS, a methodology for designing approximate arithmetic operators through ML-based supersampling. Specifically, we present a method to leverage the correlation of PPA and BEHAV metrics across operators of varying bit-widths for generating larger bit-width operators. The proposed approach involves traversing the relatively smaller design space of smaller bit-width operators and employing its associated Design-PPA-BEHAV relationship to generate initial solutions for metaheuristics-based optimization for larger operators. The experimental evaluation of AxOCS for FPGA-optimized approximate operators shows that the proposed approach significantly improves the quality-resulting hypervolume for multi-objective optimization-of 8x8 signed approximate multipliers.
format Preprint
id arxiv_https___arxiv_org_abs_2309_12830
institution arXiv
publishDate 2023
record_format arxiv
spellingShingle AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling
Sahoo, Siva Satyendra
Ullah, Salim
Bhattacharjee, Soumyo
Kumar, Akash
Hardware Architecture
Artificial Intelligence
Machine Learning
Signal Processing
B.2.4; J.6; J.7; I.2.1
The rising usage of AI and ML-based processing across application domains has exacerbated the need for low-cost ML implementation, specifically for resource-constrained embedded systems. To this end, approximate computing, an approach that explores the power, performance, area (PPA), and behavioral accuracy (BEHAV) trade-offs, has emerged as a possible solution for implementing embedded machine learning. Due to the predominance of MAC operations in ML, designing platform-specific approximate arithmetic operators forms one of the major research problems in approximate computing. Recently there has been a rising usage of AI/ML-based design space exploration techniques for implementing approximate operators. However, most of these approaches are limited to using ML-based surrogate functions for predicting the PPA and BEHAV impact of a set of related design decisions. While this approach leverages the regression capabilities of ML methods, it does not exploit the more advanced approaches in ML. To this end, we propose AxOCS, a methodology for designing approximate arithmetic operators through ML-based supersampling. Specifically, we present a method to leverage the correlation of PPA and BEHAV metrics across operators of varying bit-widths for generating larger bit-width operators. The proposed approach involves traversing the relatively smaller design space of smaller bit-width operators and employing its associated Design-PPA-BEHAV relationship to generate initial solutions for metaheuristics-based optimization for larger operators. The experimental evaluation of AxOCS for FPGA-optimized approximate operators shows that the proposed approach significantly improves the quality-resulting hypervolume for multi-objective optimization-of 8x8 signed approximate multipliers.
title AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling
topic Hardware Architecture
Artificial Intelligence
Machine Learning
Signal Processing
B.2.4; J.6; J.7; I.2.1
url https://arxiv.org/abs/2309.12830