A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
Fuente:
arXiv
Saved in:
| Main Authors: | Brignone, Giovanni, Lazarescu, Mihai T., Lavagno, Luciano |
|---|---|
| Format: | Preprint |
| Published: |
2023
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
by: Brignone, Giovanni, et al.
Published: (2024)
by: Brignone, Giovanni, et al.
Published: (2024)
Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA
by: Leon, Vasileios, et al.
Published: (2024)
by: Leon, Vasileios, et al.
Published: (2024)
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
by: Böttcher, Andreas, et al.
Published: (2024)
by: Böttcher, Andreas, et al.
Published: (2024)
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
by: Liu, Xingyu, et al.
Published: (2025)
by: Liu, Xingyu, et al.
Published: (2025)
Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
by: Li, Jindong, et al.
Published: (2024)
by: Li, Jindong, et al.
Published: (2024)
FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks
by: Leon, Vasileios, et al.
Published: (2025)
by: Leon, Vasileios, et al.
Published: (2025)
ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)
by: Li, Runkai, et al.
Published: (2025)
HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks
by: Abi-Karam, Stefan, et al.
Published: (2025)
by: Abi-Karam, Stefan, et al.
Published: (2025)
From Circuits to SoC Processors: Arithmetic Approximation Techniques & Embedded Computing Methodologies for DSP Acceleration
by: Leon, Vasileios
Published: (2023)
by: Leon, Vasileios
Published: (2023)
DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
by: Metz, David, et al.
Published: (2026)
by: Metz, David, et al.
Published: (2026)
R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges
by: Metz, David, et al.
Published: (2024)
by: Metz, David, et al.
Published: (2024)
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration
by: Ottati, Fabrizio, et al.
Published: (2023)
by: Ottati, Fabrizio, et al.
Published: (2023)
ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis
by: Peng, Zedong, et al.
Published: (2025)
by: Peng, Zedong, et al.
Published: (2025)
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
by: Ahmed, Md Rubel, et al.
Published: (2024)
by: Ahmed, Md Rubel, et al.
Published: (2024)
Stream-HLS: Towards Automatic Dataflow Acceleration
by: Basalama, Suhail, et al.
Published: (2025)
by: Basalama, Suhail, et al.
Published: (2025)
MING: An Automated CNN-to-Edge MLIR HLS framework
by: Bi, Jiahong, et al.
Published: (2026)
by: Bi, Jiahong, et al.
Published: (2026)
HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)
by: Zou, Qingyun, et al.
Published: (2025)
Efficient Task Transfer for HLS DSE
by: Ding, Zijian, et al.
Published: (2024)
by: Ding, Zijian, et al.
Published: (2024)
SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS
by: Shi, Rui, et al.
Published: (2025)
by: Shi, Rui, et al.
Published: (2025)
Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)
by: Ifrim, Rares, et al.
Published: (2025)
Just TestIt! An SBST Approach To Automate System-Integration Testing
by: Terzano, Tommaso, et al.
Published: (2025)
by: Terzano, Tommaso, et al.
Published: (2025)
DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics
by: Cao, Yingqi, et al.
Published: (2024)
by: Cao, Yingqi, et al.
Published: (2024)
RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs
by: Kim, Jiho, et al.
Published: (2025)
by: Kim, Jiho, et al.
Published: (2025)
ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools
by: Wanna, Andy, et al.
Published: (2025)
by: Wanna, Andy, et al.
Published: (2025)
Iceberg: Enhancing HLS Modeling with Synthetic Data
by: Ding, Zijian, et al.
Published: (2025)
by: Ding, Zijian, et al.
Published: (2025)
System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)
by: Liao, Yuchao, et al.
Published: (2024)
Low-Level and NUMA-Aware Optimization for High-Performance Quantum Simulation
by: Rezaei, Ali, et al.
Published: (2025)
by: Rezaei, Ali, et al.
Published: (2025)
Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures enabled by Non-bendable Glass Interposer
by: Sharma, Harsh, et al.
Published: (2025)
by: Sharma, Harsh, et al.
Published: (2025)
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025)
by: Abi-Karam, Stefan, et al.
Published: (2025)
Low-Cost IoT-Enabled Tele-ECG Monitoring for Resource-Constrained Settings: System Design and Prototype
by: Neupane, Seemron, et al.
Published: (2026)
by: Neupane, Seemron, et al.
Published: (2026)
FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
by: Zhang, Jiahao, et al.
Published: (2026)
by: Zhang, Jiahao, et al.
Published: (2026)
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
by: Ho, Chia-Tung, et al.
Published: (2025)
by: Ho, Chia-Tung, et al.
Published: (2025)
Tools and Methodologies for System-Level Design
by: Bhattacharyya, Shuvra S., et al.
Published: (2025)
by: Bhattacharyya, Shuvra S., et al.
Published: (2025)
A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization
by: Zhang, Yifan, et al.
Published: (2025)
by: Zhang, Yifan, et al.
Published: (2025)
Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
by: Khan, M Zafir Sadik, et al.
Published: (2026)
by: Khan, M Zafir Sadik, et al.
Published: (2026)
A Paradigm for Generalized Multi-Level Priority Encoders
by: Phillips, Maxwell, et al.
Published: (2026)
by: Phillips, Maxwell, et al.
Published: (2026)
Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory
by: Fan, Keming, et al.
Published: (2024)
by: Fan, Keming, et al.
Published: (2024)
MPM-LLM4DSE: Reaching the Pareto Frontier in HLS with Multimodal Learning and LLM-Driven Exploration
by: Xu, Lei, et al.
Published: (2026)
by: Xu, Lei, et al.
Published: (2026)
DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits
by: Ardakani, Arash, et al.
Published: (2025)
by: Ardakani, Arash, et al.
Published: (2025)
Deep Inverse Design for High-Level Synthesis
by: Chang, Ping, et al.
Published: (2024)
by: Chang, Ping, et al.
Published: (2024)
Similar Items
-
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
by: Brignone, Giovanni, et al.
Published: (2024) -
Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA
by: Leon, Vasileios, et al.
Published: (2024) -
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
by: Böttcher, Andreas, et al.
Published: (2024) -
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
by: Liu, Xingyu, et al.
Published: (2025) -
Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
by: Li, Jindong, et al.
Published: (2024)