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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2310.01336 |
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| _version_ | 1866914046354128896 |
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| author | Houraniah, Ahmad Ugurdag, H. Fatih Aydin, Furkan |
| author_facet | Houraniah, Ahmad Ugurdag, H. Fatih Aydin, Furkan |
| contents | Reducing a set of numbers to a single value is a fundamental operation in applications such as signal processing, data compression, scientific computing, and neural networks. Accumulation, which involves summing a dataset to obtain a single result, is crucial for these tasks. Due to hardware constraints, large vectors or matrices often cannot be fully stored in memory and must be read sequentially, one item per clock cycle. For high-speed inputs, such as rapidly arriving floating-point numbers, pipelined adders are necessary to maintain performance. However, pipelining introduces multiple intermediate sums and requires delays between back-to-back datasets unless their processing is overlapped. In this paper, we present JugglePAC, a novel accumulation circuit designed to address these challenges. JugglePAC operates quickly, is area-efficient, and features a fully pipelined design. It effectively manages back-to-back variable-length datasets while consistently producing results in the correct input order. Compared to the state-of-the-art, JugglePAC achieves higher throughput and reduces area complexity, offering significant improvements in performance and efficiency. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2310_01336 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | JugglePAC: A Pipelined Accumulation Circuit Houraniah, Ahmad Ugurdag, H. Fatih Aydin, Furkan Hardware Architecture Reducing a set of numbers to a single value is a fundamental operation in applications such as signal processing, data compression, scientific computing, and neural networks. Accumulation, which involves summing a dataset to obtain a single result, is crucial for these tasks. Due to hardware constraints, large vectors or matrices often cannot be fully stored in memory and must be read sequentially, one item per clock cycle. For high-speed inputs, such as rapidly arriving floating-point numbers, pipelined adders are necessary to maintain performance. However, pipelining introduces multiple intermediate sums and requires delays between back-to-back datasets unless their processing is overlapped. In this paper, we present JugglePAC, a novel accumulation circuit designed to address these challenges. JugglePAC operates quickly, is area-efficient, and features a fully pipelined design. It effectively manages back-to-back variable-length datasets while consistently producing results in the correct input order. Compared to the state-of-the-art, JugglePAC achieves higher throughput and reduces area complexity, offering significant improvements in performance and efficiency. |
| title | JugglePAC: A Pipelined Accumulation Circuit |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2310.01336 |