Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm
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arXiv
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| Hauptverfasser: | , |
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| Format: | Preprint |
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2023
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| _version_ | 1866913192017395712 |
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| author | Rogenmoser, Michael Benini, Luca |
| author_facet | Rogenmoser, Michael Benini, Luca |
| contents | One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2310_02045 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm Rogenmoser, Michael Benini, Luca Hardware Architecture One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency. |
| title | Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2310.02045 |