A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI
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arXiv
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| Main Authors: | , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2023
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| _version_ | 1866916110654242816 |
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| author | Bauer, Heiner Stolba, Marco Scholze, Stefan Walter, Dennis Mayr, Christian Oefelein, Alexander Höppner, Sebastian Scharfe, André Schraut, Flo Eisenreich, Holger |
| author_facet | Bauer, Heiner Stolba, Marco Scholze, Stefan Walter, Dennis Mayr, Christian Oefelein, Alexander Höppner, Sebastian Scharfe, André Schraut, Flo Eisenreich, Holger |
| contents | We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by using an adaptive reverse body biasing aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from -40 °C to 125 °C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2310_09094 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI Bauer, Heiner Stolba, Marco Scholze, Stefan Walter, Dennis Mayr, Christian Oefelein, Alexander Höppner, Sebastian Scharfe, André Schraut, Flo Eisenreich, Holger Hardware Architecture We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by using an adaptive reverse body biasing aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from -40 °C to 125 °C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode. |
| title | A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2310.09094 |