Chameleon: a Heterogeneous and Disaggregated Accelerator System for Retrieval-Augmented Language Models
Fuente:
arXiv
Guardado en:
| Autores principales: | Jiang, Wenqi, Zeller, Marco, Waleffe, Roger, Hoefler, Torsten, Alonso, Gustavo |
|---|---|
| Formato: | Preprint |
| Publicado: |
2023
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Fast Graph Vector Search via Hardware Acceleration and Delayed-Synchronization Traversal
por: Jiang, Wenqi, et al.
Publicado: (2024)
por: Jiang, Wenqi, et al.
Publicado: (2024)
HADES: Hardware Accelerated Decoding for Efficient Speculation in Large Language Models
por: Yang, Ze, et al.
Publicado: (2024)
por: Yang, Ze, et al.
Publicado: (2024)
Accelerating Retrieval-Augmented Generation
por: Quinn, Derrick, et al.
Publicado: (2024)
por: Quinn, Derrick, et al.
Publicado: (2024)
LLM Inference Acceleration via Efficient Operation Fusion
por: Salmani, Mahsa, et al.
Publicado: (2025)
por: Salmani, Mahsa, et al.
Publicado: (2025)
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
por: Xing, Changwen, et al.
Publicado: (2025)
por: Xing, Changwen, et al.
Publicado: (2025)
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures
por: Curzel, Serena, et al.
Publicado: (2023)
por: Curzel, Serena, et al.
Publicado: (2023)
Heterogeneous Acceleration Pipeline for Recommendation System Training
por: Adnan, Muhammad, et al.
Publicado: (2022)
por: Adnan, Muhammad, et al.
Publicado: (2022)
From English to ASIC: Hardware Implementation with Large Language Model
por: Goh, Emil, et al.
Publicado: (2024)
por: Goh, Emil, et al.
Publicado: (2024)
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference
por: Chen, Hongzheng, et al.
Publicado: (2023)
por: Chen, Hongzheng, et al.
Publicado: (2023)
Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System
por: Fang, Yunhua, et al.
Publicado: (2025)
por: Fang, Yunhua, et al.
Publicado: (2025)
EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD
por: Wu, Bing-Yue, et al.
Publicado: (2024)
por: Wu, Bing-Yue, et al.
Publicado: (2024)
DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model
por: Chen, Hong Cai, et al.
Publicado: (2024)
por: Chen, Hong Cai, et al.
Publicado: (2024)
LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code Generation
por: Wu, Yuheng, et al.
Publicado: (2026)
por: Wu, Yuheng, et al.
Publicado: (2026)
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge
por: Fu, Weimin, et al.
Publicado: (2024)
por: Fu, Weimin, et al.
Publicado: (2024)
Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators
por: Müller, Mika Markus, et al.
Publicado: (2024)
por: Müller, Mika Markus, et al.
Publicado: (2024)
DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
por: Ibnat, Zahin, et al.
Publicado: (2025)
por: Ibnat, Zahin, et al.
Publicado: (2025)
Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
por: Barocci, Michelangelo, et al.
Publicado: (2026)
por: Barocci, Michelangelo, et al.
Publicado: (2026)
HALO: Memory-Centric Heterogeneous Accelerator with 2.5D Integration for Low-Batch LLM Inference
por: Negi, Shubham, et al.
Publicado: (2025)
por: Negi, Shubham, et al.
Publicado: (2025)
Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference
por: Chen, Chun-Ting, et al.
Publicado: (2025)
por: Chen, Chun-Ting, et al.
Publicado: (2025)
EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models
por: Bazzi, Jinane, et al.
Publicado: (2026)
por: Bazzi, Jinane, et al.
Publicado: (2026)
ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols
por: Sheth, Arnav, et al.
Publicado: (2025)
por: Sheth, Arnav, et al.
Publicado: (2025)
TriGen: NPU Architecture for End-to-End Acceleration of Large Language Models based on SW-HW Co-Design
por: Lee, Jonghun, et al.
Publicado: (2026)
por: Lee, Jonghun, et al.
Publicado: (2026)
FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
por: Iff, Patrick, et al.
Publicado: (2025)
por: Iff, Patrick, et al.
Publicado: (2025)
Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
por: Xu, Haocheng, et al.
Publicado: (2024)
por: Xu, Haocheng, et al.
Publicado: (2024)
InCoder-32B-Thinking: Industrial Code World Model for Thinking
por: Yang, Jian, et al.
Publicado: (2026)
por: Yang, Jian, et al.
Publicado: (2026)
ProactivePIM: Accelerating Weight-Sharing Embedding Layer with PIM for Scalable Recommendation System
por: Kim, Youngsuk, et al.
Publicado: (2024)
por: Kim, Youngsuk, et al.
Publicado: (2024)
An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems
por: Antonio, Ryan Albert, et al.
Publicado: (2025)
por: Antonio, Ryan Albert, et al.
Publicado: (2025)
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
por: Wang, Ning, et al.
Publicado: (2024)
por: Wang, Ning, et al.
Publicado: (2024)
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
por: Yao, Bingkun, et al.
Publicado: (2024)
por: Yao, Bingkun, et al.
Publicado: (2024)
Autocomp: A Powerful and Portable Code Optimizer for Tensor Accelerators
por: Hong, Charles, et al.
Publicado: (2025)
por: Hong, Charles, et al.
Publicado: (2025)
Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language
por: Wang, Runzhi, et al.
Publicado: (2025)
por: Wang, Runzhi, et al.
Publicado: (2025)
MARCA: Mamba Accelerator with ReConfigurable Architecture
por: Li, Jinhao, et al.
Publicado: (2024)
por: Li, Jinhao, et al.
Publicado: (2024)
Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models
por: Sandal, Selim, et al.
Publicado: (2024)
por: Sandal, Selim, et al.
Publicado: (2024)
ChipGPT: How far are we from natural language hardware design
por: Chang, Kaiyan, et al.
Publicado: (2023)
por: Chang, Kaiyan, et al.
Publicado: (2023)
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
por: Zhao, Jiayu, et al.
Publicado: (2025)
por: Zhao, Jiayu, et al.
Publicado: (2025)
Digital ASIC Design with Ongoing LLMs: Strategies and Prospects
por: Xiang, Maoyang, et al.
Publicado: (2024)
por: Xiang, Maoyang, et al.
Publicado: (2024)
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
por: Chen, Zhirong, et al.
Publicado: (2025)
por: Chen, Zhirong, et al.
Publicado: (2025)
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
por: Vijayaraghavan, Prashanth, et al.
Publicado: (2025)
por: Vijayaraghavan, Prashanth, et al.
Publicado: (2025)
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
por: Blocklove, Jason, et al.
Publicado: (2024)
por: Blocklove, Jason, et al.
Publicado: (2024)
GPU Performance Portability needs Autotuning
por: Ringlein, Burkhard, et al.
Publicado: (2025)
por: Ringlein, Burkhard, et al.
Publicado: (2025)
Ejemplares similares
-
Fast Graph Vector Search via Hardware Acceleration and Delayed-Synchronization Traversal
por: Jiang, Wenqi, et al.
Publicado: (2024) -
HADES: Hardware Accelerated Decoding for Efficient Speculation in Large Language Models
por: Yang, Ze, et al.
Publicado: (2024) -
Accelerating Retrieval-Augmented Generation
por: Quinn, Derrick, et al.
Publicado: (2024) -
LLM Inference Acceleration via Efficient Operation Fusion
por: Salmani, Mahsa, et al.
Publicado: (2025) -
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
por: Xing, Changwen, et al.
Publicado: (2025)