PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2023
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| _version_ | 1866909076447821824 |
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| author | Ottaviano, Alessandro Balas, Robert Sauter, Philippe Eggimann, Manuel Benini, Luca |
| author_facet | Ottaviano, Alessandro Balas, Robert Sauter, Philippe Eggimann, Manuel Benini, Luca |
| contents | A key challenge for ultra-low-power (ULP) devices is handling peripheral linking, where the main central processing unit (CPU) periodically mediates the interaction among multiple peripherals following wake-up events. Current solutions address this problem by either integrating event interconnects that route single-wire event lines among peripherals or by general-purpose I/O processors, with a strong trade-off between the latency, efficiency of the former, and the flexibility of the latter. In this paper, we present an open-source, peripheral-agnostic, lightweight, and flexible Peripheral Event Linking System (PELS) that combines dedicated event routing with a tiny I/O processor. With the proposed approach, the power consumption of a linking event is reduced by 2.5 times compared to a baseline relying on the main core for the event-linking process, at a low area of just 7 kGE in its minimal configuration, when integrated into a ULP RISC-V IoT processor. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2311_09645 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors Ottaviano, Alessandro Balas, Robert Sauter, Philippe Eggimann, Manuel Benini, Luca Hardware Architecture A key challenge for ultra-low-power (ULP) devices is handling peripheral linking, where the main central processing unit (CPU) periodically mediates the interaction among multiple peripherals following wake-up events. Current solutions address this problem by either integrating event interconnects that route single-wire event lines among peripherals or by general-purpose I/O processors, with a strong trade-off between the latency, efficiency of the former, and the flexibility of the latter. In this paper, we present an open-source, peripheral-agnostic, lightweight, and flexible Peripheral Event Linking System (PELS) that combines dedicated event routing with a tiny I/O processor. With the proposed approach, the power consumption of a linking event is reduced by 2.5 times compared to a baseline relying on the main core for the event-linking process, at a low area of just 7 kGE in its minimal configuration, when integrated into a ULP RISC-V IoT processor. |
| title | PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2311.09645 |