Efficient and Scalable Architecture for Multiple-chip Implementation of Simulated Bifurcation Machines

Fuente: arXiv

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Bibliographic Details
Main Authors:	Kashimata, Tomoya, Yamasaki, Masaya, Hidaka, Ryo, Tatsumura, Kosuke
Format:	Preprint
Published:	2023
Subjects:	Emerging Technologies Hardware Architecture Distributed, Parallel, and Cluster Computing Performance 68M20 C.3; C.5.4
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2311.17370