Ellora: Exploring Low-Power OFDM-based Radar Processors using Approximate Computing
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2023
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| _version_ | 1866912069657296896 |
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| author | Bhattacharjya, Rajat Kanani, Alish Kumar, A Anil Nambiar, Manoj Chandra, M Girish Singhal, Rekha |
| author_facet | Bhattacharjya, Rajat Kanani, Alish Kumar, A Anil Nambiar, Manoj Chandra, M Girish Singhal, Rekha |
| contents | In recent times, orthogonal frequency-division multiplexing (OFDM)-based radar has gained wide acceptance given its applicability in joint radar-communication systems. However, realizing such a system on hardware poses a huge area and power bottleneck given its complexity. Therefore it has become ever-important to explore low-power OFDM-based radar processors in order to realize energy-efficient joint radar-communication systems targeting edge devices. This paper aims to address the aforementioned challenges by exploiting approximations on hardware for early design space exploration (DSE) of trade-offs between accuracy, area and power. We present Ellora, a DSE framework for incorporating approximations in an OFDM radar processing pipeline. Ellora uses pairs of approximate adders and multipliers to explore design points realizing energy-efficient radar processors. Particularly, we incorporate approximations into the block involving periodogram based estimation and report area, power and accuracy levels. Experimental results show that at an average accuracy loss of 0.063% in the positive SNR region, we save 22.9% of on-chip area and 26.2% of power. Towards achieving the area and power statistics, we design a fully parallel Inverse Fast Fourier Transform (IFFT) core which acts as a part of periodogram based estimation and approximate the addition and multiplication operations in it. The aforementioned results show that Ellora can be used in an integrated way with various other optimization methods for generating low-power and energy-efficient radar processors. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2312_00176 |
| institution | arXiv |
| publishDate | 2023 |
| record_format | arxiv |
| spellingShingle | Ellora: Exploring Low-Power OFDM-based Radar Processors using Approximate Computing Bhattacharjya, Rajat Kanani, Alish Kumar, A Anil Nambiar, Manoj Chandra, M Girish Singhal, Rekha Hardware Architecture Signal Processing In recent times, orthogonal frequency-division multiplexing (OFDM)-based radar has gained wide acceptance given its applicability in joint radar-communication systems. However, realizing such a system on hardware poses a huge area and power bottleneck given its complexity. Therefore it has become ever-important to explore low-power OFDM-based radar processors in order to realize energy-efficient joint radar-communication systems targeting edge devices. This paper aims to address the aforementioned challenges by exploiting approximations on hardware for early design space exploration (DSE) of trade-offs between accuracy, area and power. We present Ellora, a DSE framework for incorporating approximations in an OFDM radar processing pipeline. Ellora uses pairs of approximate adders and multipliers to explore design points realizing energy-efficient radar processors. Particularly, we incorporate approximations into the block involving periodogram based estimation and report area, power and accuracy levels. Experimental results show that at an average accuracy loss of 0.063% in the positive SNR region, we save 22.9% of on-chip area and 26.2% of power. Towards achieving the area and power statistics, we design a fully parallel Inverse Fast Fourier Transform (IFFT) core which acts as a part of periodogram based estimation and approximate the addition and multiplication operations in it. The aforementioned results show that Ellora can be used in an integrated way with various other optimization methods for generating low-power and energy-efficient radar processors. |
| title | Ellora: Exploring Low-Power OFDM-based Radar Processors using Approximate Computing |
| topic | Hardware Architecture Signal Processing |
| url | https://arxiv.org/abs/2312.00176 |