Cover Image

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Liu, Shang, Fang, Wenji, Lu, Yao, Zhang, Qijun, Zhang, Hongce, Xie, Zhiyao
Format:	Preprint
Published:	2023
Subjects:	Programming Languages Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
by: Fang, Wenji, et al.
Published: (2025)

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Yan, Zhiyuan, et al.
Published: (2024)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Fang, Wenji, et al.
Published: (2024)

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
by: Li, Wenkai, et al.
Published: (2025)

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
by: Zhang, Qijun, et al.
Published: (2025)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
by: Fang, Wenji, et al.
Published: (2025)

Profile-Guided Temporal Prefetching
by: Li, Mengming, et al.
Published: (2025)

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
by: Zhang, Qijun, et al.
Published: (2025)

Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
by: Zhang, Qijun, et al.
Published: (2024)

AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
by: Zhang, Qijun, et al.
Published: (2025)

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
by: Fang, Wenji, et al.
Published: (2025)

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
by: Zhang, Qijun, et al.
Published: (2024)

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
by: Fang, Wenji, et al.
Published: (2025)

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025)

AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
by: Wu, Yuchao, et al.
Published: (2026)

GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
by: Li, Mengming, et al.
Published: (2026)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
by: Zhou, Jie, et al.
Published: (2025)

Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
by: Chao, Zhiteng, et al.
Published: (2025)

AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking
by: Hu, Guangyu, et al.
Published: (2026)

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
by: Chen, Chen, et al.
Published: (2025)

UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)

EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning
by: Hu, Guangyu, et al.
Published: (2026)

LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)

Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
by: Shao, Minghao, et al.
Published: (2026)

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)

Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
by: Zoni, Davide, et al.
Published: (2025)

Assessing Large Language Models in Generating RTL Design Specifications
by: Huang, Hung-Ming, et al.
Published: (2025)

BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning
by: Miao, Mingkai, et al.
Published: (2025)

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)

Automated Multi-Agent Workflows for RTL Design
by: Bhattaram, Amulya, et al.
Published: (2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)