MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Fuente: arXiv

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Bibliographic Details
Main Authors:	Perotti, Matteo, Zhang, Yichao, Cavalcante, Matheus, Mustafa, Enis, Benini, Luca
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2401.04012