:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Magliano, Enrico, Carpegna, Alessio, Savino, Alessadro, Di Carlo, Stefano
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	https://arxiv.org/abs/2401.08397
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge
by: Carpegna, Alessio, et al.
Published: (2024)

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures
by: Curzel, Serena, et al.
Published: (2023)

Achieving Trustworthy Real-Time Decision Support Systems with Low-Latency Interpretable AI Models
by: Deng, Zechun, et al.
Published: (2025)

FPGA Resource-aware Structured Pruning for Real-Time Neural Networks
by: Ramhorst, Benjamin, et al.
Published: (2023)

Monitor Placement for Fault Localization in Deep Neural Network Accelerators
by: Liu, Wei-Kai
Published: (2023)

ProactivePIM: Accelerating Weight-Sharing Embedding Layer with PIM for Scalable Recommendation System
by: Kim, Youngsuk, et al.
Published: (2024)

ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models
by: Lv, Wenhao, et al.
Published: (2025)

Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays
by: Jeon, Kang Eun, et al.
Published: (2025)

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
by: Barocci, Michelangelo, et al.
Published: (2026)

MicroScopiQ: Accelerating Foundational Models through Outlier-Aware Microscaling Quantization
by: Ramachandran, Akshat, et al.
Published: (2024)

MARCA: Mamba Accelerator with ReConfigurable Architecture
by: Li, Jinhao, et al.
Published: (2024)

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
by: Jaswal, Pragun, et al.
Published: (2026)

BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration
by: Rakka, Mariam, et al.
Published: (2024)

Design Space Exploration of Approximate Computing Techniques with a Reinforcement Learning Approach
by: Saeedi, Sepide, et al.
Published: (2023)

PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs
by: Malekar, Jinendra, et al.
Published: (2025)

Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review
by: Chatterjee, Soumita, et al.
Published: (2026)

Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
by: Sharma, Harsh, et al.
Published: (2024)

FractalCloud: A Fractal-Inspired Architecture for Efficient Large-Scale Point Cloud Processing
by: Fu, Yuzhe, et al.
Published: (2025)

ELSA: An ELastic SNN Inference Architecture for Efficient Neuromorphic Computing
by: You, Kang, et al.
Published: (2026)

Low Power Approximate Multiplier Architecture for Deep Neural Networks
by: Jaswal, Pragun, et al.
Published: (2025)

Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
by: Xu, Zhexuan, et al.
Published: (2025)

Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture
by: Deng, Jinyi, et al.
Published: (2024)

LUMINA: LLM-Guided GPU Architecture Exploration via Bottleneck Analysis
by: Zhang, Tao, et al.
Published: (2026)

Agentic Architect: An Agentic AI Framework for Architecture Design Exploration and Optimization
by: Blasberg, Alexander, et al.
Published: (2026)

Exploiting the Vulnerability of Large Language Models via Defense-Aware Architectural Backdoor
by: Miah, Abdullah Arafat, et al.
Published: (2024)

A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning
by: Jhonsa, Jinesh, et al.
Published: (2025)

Embedded FPGA Acceleration of Brain-Like Neural Networks: Online Learning to Scalable Inference
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2025)

ALADIN: Accuracy-Latency-Aware Design-space Inference Analysis for Embedded AI Accelerators
by: Baldi, T., et al.
Published: (2026)

Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators
by: Müller, Mika Markus, et al.
Published: (2024)

Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture
by: Wan, Zishen, et al.
Published: (2024)

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
by: Zhang, Qijun, et al.
Published: (2025)

HiAER-Spike Software-Hardware Reconfigurable Platform for Event-Driven Neuromorphic Computing at Scale
by: Frank, Gwenevere, et al.
Published: (2026)

Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator
by: Tyagi, Abhishek, et al.
Published: (2024)

CiMNet: Towards Joint Optimization for DNN Architecture and Configuration for Compute-In-Memory Hardware
by: Kundu, Souvik, et al.
Published: (2024)

Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization
by: Lou, Binglei, et al.
Published: (2026)

AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices
by: Zirui, Ma, et al.
Published: (2026)

DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP
by: Li, Guoyu, et al.
Published: (2025)

Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decoding
by: Fan, Wang, et al.
Published: (2026)

Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
by: Liu, Yuhao, et al.
Published: (2026)

EDA-Aware RTL Generation with Large Language Models
by: Islam, Mubashir ul, et al.
Published: (2024)