Floating Point HUB Adder for RISC-V Sargantana Processor
Fuente:
arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| Soggetti: | |
| Accesso online: | |
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| _version_ | 1866929213169205248 |
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| author | Bandera, Gerardo Salamero, Javier Moreto, Miquel Villalba, Julio |
| author_facet | Bandera, Gerardo Salamero, Javier Moreto, Miquel Villalba, Julio |
| contents | HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is an open-source ISA that many companies currently use in their designs. This paper presents a tailored floating point HUB adder implemented in the Sargantana RISC-V processor. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2401_09464 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Floating Point HUB Adder for RISC-V Sargantana Processor Bandera, Gerardo Salamero, Javier Moreto, Miquel Villalba, Julio Hardware Architecture HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is an open-source ISA that many companies currently use in their designs. This paper presents a tailored floating point HUB adder implemented in the Sargantana RISC-V processor. |
| title | Floating Point HUB Adder for RISC-V Sargantana Processor |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2401.09464 |