Copertina

A Survey on Hardware Accelerators for Large Language Models

Fuente: arXiv

Salvato in:

Dettagli Bibliografici
Autore principale:	Kachris, Christoforos
Natura:	Preprint
Pubblicazione:	2024
Soggetti:	Hardware Architecture Computation and Language Machine Learning B.5; C.1; C.3
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

Documenti analoghi

Design and Implementation of an FPGA-Based Hardware Accelerator for Transformer
di: Li, Richie, et al.
Pubblicazione: (2025)

Weight Block Sparsity: Training, Compilation, and AI Engine Accelerators
di: D'Alberto, Paolo, et al.
Pubblicazione: (2024)

LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference
di: Mo, Zhiwen, et al.
Pubblicazione: (2024)

Hardware Acceleration of LLMs: A comprehensive survey and comparison
di: Koilia, Nikoletta, et al.
Pubblicazione: (2024)

HEPPO-GAE: Hardware-Efficient Proximal Policy Optimization with Generalized Advantage Estimation
di: Taha, Hazem, et al.
Pubblicazione: (2025)

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
di: Parameshwara, Arya, et al.
Pubblicazione: (2025)

Mestra: Exploring Migration on Virtualized CGRAs
di: Kyriazis, Agamemnon, et al.
Pubblicazione: (2026)

RayFlex: An Open-Source RTL Implementation of the Hardware Ray Tracer Datapath
di: Shen, Fangjia, et al.
Pubblicazione: (2024)

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
di: Yildirim, Muhammed, et al.
Pubblicazione: (2025)

FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review
di: Jiang, Junye, et al.
Pubblicazione: (2025)

A WASM-Subset Stack Architecture for Low-cost FPGAs using Open-Source EDA Flows
di: Chakrabarti, Aradhya
Pubblicazione: (2025)

Anvil: A General-Purpose Timing-Safe Hardware Description Language
di: Yu, Jason Zhijingcheng, et al.
Pubblicazione: (2025)

OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
di: Lebold, Denis, et al.
Pubblicazione: (2026)

Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures
di: Siracusa, Marco, et al.
Pubblicazione: (2025)

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
di: Aspros, Maxime Henri, et al.
Pubblicazione: (2025)

Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories
di: Lee, Ming-Yen, et al.
Pubblicazione: (2025)

Improved Prefetching Techniques for Linked Data Structures
di: Maruszewski, Nikola Vuk
Pubblicazione: (2025)

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
di: Yadav, Priyanshu
Pubblicazione: (2025)

Exploring the Design Space for Message-Driven Systems for Dynamic Graph Processing using CCA
di: Chandio, Bibrak Qamar, et al.
Pubblicazione: (2024)

Toward a Universal GPU Instruction Set Architecture: A Cross-Vendor Analysis of Hardware-Invariant Computational Primitives in Parallel Processors
di: Abraham, Ojima, et al.
Pubblicazione: (2026)

IPU: Flexible Hardware Introspection Units
di: McDougall, Ian, et al.
Pubblicazione: (2023)

DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
di: Zhang, Yuhan, et al.
Pubblicazione: (2026)

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms
di: Taji, Hossein, et al.
Pubblicazione: (2025)

SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
di: Parameshwara, Arya
Pubblicazione: (2025)

OPAL: Outlier-Preserved Microscaling Quantization Accelerator for Generative Large Language Models
di: Koo, Jahyun, et al.
Pubblicazione: (2024)

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads
di: Suryadevara, Pranav
Pubblicazione: (2025)

Chameleon: A MatMul-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data
di: Blanken, Douwe den, et al.
Pubblicazione: (2025)

D-com: Accelerating Iterative Processing to Enable Low-rank Decomposition of Activations
di: Tahmasebi, Faraz, et al.
Pubblicazione: (2025)

Biological Intuition on Digital Hardware: An RTL Implementation of Poisson-Encoded SNNs for Static Image Classification
di: Das, Debabrata, et al.
Pubblicazione: (2026)

InterPUF: Distributed Authentication via Physically Unclonable Functions and Multi-party Computation for Reconfigurable Interposers
di: Tashdid, Ishraq, et al.
Pubblicazione: (2026)

Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing
di: Mitra, Subhasish, et al.
Pubblicazione: (2025)

C for a tiny system
di: Krause, Philipp Klaus, et al.
Pubblicazione: (2020)

SISA: A Scale-In Systolic Array for GEMM Acceleration
di: Altamura, Luigi, et al.
Pubblicazione: (2026)

A Flexible Instruction Set Architecture for Efficient GEMMs
di: Santana, Alexandre de Limas, et al.
Pubblicazione: (2025)

Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning
di: Yuan, Aojie, et al.
Pubblicazione: (2026)

Fast and Practical Strassen's Matrix Multiplication using FPGAs
di: Ahmad, Afzal, et al.
Pubblicazione: (2024)

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM
di: Liu, Lian, et al.
Pubblicazione: (2025)

FlexiBit: Fully Flexible Precision Bit-parallel Accelerator Architecture for Arbitrary Mixed Precision AI
di: Tahmasebi, Faraz, et al.
Pubblicazione: (2024)

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
di: Ferreira, João Dinis, et al.
Pubblicazione: (2021)

AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
di: Nguyen, Van Tinh, et al.
Pubblicazione: (2025)