Cover Image

Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Zang, Zhenya, Dolinsky, Uwe, Ghiglio, Pietro, Cherubin, Stefano, Goli, Mehdi, Yang, Shufan
Format:	Preprint
Published:	2023
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors
by: Behboudi, Noushin, et al.
Published: (2024)

Online Learning Extreme Learning Machine with Low-Complexity Predictive Plasticity Rule and FPGA Implementation
by: Zang, Zhenya, et al.
Published: (2025)

An FPGA Compiler for On-the-Fly Adaptive CNN Deployment and Reconfiguration
by: Mazouz, Alaa, et al.
Published: (2025)

Capstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers
by: Yarzada, Sabrina, et al.
Published: (2026)

Algorithms for Improving the Automatically Synthesized Instruction Set of an Extensible Processor
by: Sovietov, Peter
Published: (2024)

CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms
by: Khan, Asif Ali, et al.
Published: (2022)

DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2022)

SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support
by: Diao, Haikang, et al.
Published: (2025)

HiHGNN: Accelerating HGNNs through Parallelism and Data Reusability Exploitation
by: Xue, Runzhen, et al.
Published: (2023)

A Novel Extensible Simulation Framework for CXL-Enabled Systems
by: An, Yuda, et al.
Published: (2024)

NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures
by: Li, Shangkun, et al.
Published: (2026)

ACT: Automatically Generating Compiler Backends from Tensor Accelerator ISA Descriptions
by: Jain, Devansh, et al.
Published: (2025)

Revet: A Language and Compiler for Dataflow Threads
by: Rucker, Alexander, et al.
Published: (2023)

Reconfigurable Stream Network Architecture
by: Wang, Chengyue, et al.
Published: (2024)

CODO: An Automated Compiler for Comprehensive Dataflow Optimization
by: Zhang, Weichuang, et al.
Published: (2026)

Compilation and Execution of an Embeddable YOLO-NAS on the VTA
by: Faure-Gignoux, Anthony, et al.
Published: (2026)

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project
by: Agosta, Giovanni, et al.
Published: (2025)

Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration
by: Shahawy, Mohamed, et al.
Published: (2025)

A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
by: Yang, Junyi, et al.
Published: (2026)

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
by: Chen, Xingzhen, et al.
Published: (2026)

PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators
by: Sun, Xiaotian, et al.
Published: (2024)

ATLAAS: Automatic Tensor-Level Abstraction of Accelerator Semantics
by: Gao, Ruijie, et al.
Published: (2026)

LUTstructions: Self-loading FPGA-based Reconfigurable Instructions
by: Papaphilippou, Philippos
Published: (2026)

Reconfigurable Digital RRAM Logic Enables In-Situ Pruning and Learning for Edge AI
by: Wang, Songqi, et al.
Published: (2025)

Mapping code on Coarse Grained Reconfigurable Arrays using a SAT solver
by: Tirelli, Cristian, et al.
Published: (2025)

A Dataflow Compiler for Efficient LLM Inference using Custom Microscaling Formats
by: Cheng, Jianyi, et al.
Published: (2023)

OpenACM: An Open-Source SRAM-Based Approximate CiM Compiler
by: Zhou, Yiqi, et al.
Published: (2026)

From PyTorch to Calyx: An Open-Source Compiler Toolchain for ML Accelerators
by: Xie, Jiahan, et al.
Published: (2025)

Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators
by: Zhao, Shixin, et al.
Published: (2025)

Evolution, Challenges, and Optimization in Computer Architecture: The Role of Reconfigurable Systems
by: Ederhion, Jefferson, et al.
Published: (2024)

A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
by: Yunusoglu, Aybars, et al.
Published: (2026)

Hardware-Aware DNN Compression for Homogeneous Edge Devices
by: Zhang, Kunlong, et al.
Published: (2025)

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions
by: Yang, Moucheng, et al.
Published: (2025)

Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning
by: Mishty, Kaniz, et al.
Published: (2024)

Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip
by: Zaeemi, Meysam, et al.
Published: (2026)

SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis
by: Shao, Kunming, et al.
Published: (2024)

TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
by: Guan, Yue, et al.
Published: (2026)

Tensor Manipulation Unit (TMU): Reconfigurable, Near-Memory Tensor Manipulation for High-Throughput AI SoC
by: Zhou, Weiyu, et al.
Published: (2025)

A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators
by: Li, Cong, et al.
Published: (2026)

Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
by: Biglari, Siamak, et al.
Published: (2024)